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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

598 topics in this forum

  1. Learning System Verilog from scratch

    By Dexy10,
    • 1 reply
    • 757 views

  2. Verilog/SystemVerilog Configuration default liblist question

    By cliffc,   
    • 2 replies
    • 2.4k views

  3. Verilog bug issue

    By Tarzan,
    • 2 replies
    • 568 views

  4. How to access register file array data using bind module

    By Dina Emadeldin,
    • 1 reply
    • 1.3k views

  5. Array of covergroup wrapper objects. Problems.

    By ljepson74,   
    • 1 reply
    • 3.2k views

  6. Consequence of not to be an "assignment-like context"

    By Thomas Kruse,
    • 0 replies
    • 569 views

  7. "uvm sequence library" vs "virtual sequence"

    By Nadun,   
    • 1 reply
    • 1.4k views

  8. $system() function return value OR Setting a random sim seed within SystemVerilog code using wallclock time.

    By ljepson74,   
    • 8 replies
    • 4.7k views

  9. SeqA |-> SeqA may not happen again before the first of SeqB or SeqC

    By ljepson74,   
    • 0 replies
    • 588 views

  10. “dist”. Can a value_range be a list in a randomization distribution?

    By ljepson74,   
    • 0 replies
    • 1.7k views

  11. SVA: implication vs. sequence. implication and delay.

    By ljepson74,   
    • 0 replies
    • 741 views

  12. randomize() with inside syntax

    By ljepson74,   
    • 4 replies
    • 50.5k views

  13. Constraint across properties of array of objects

    By ljepson74,   
    • 5 replies
    • 2.2k views

  14. UVM : transaction class and sequence_item class

    By Vinod_V,   
    • 0 replies
    • 852 views

  15. Explicit Prediction of Unmapped Registers

    By Henry,
    • 4 replies
    • 1.6k views

  16. Need help on agent architecture

    By santhosh2020,
    • 1 reply
    • 557 views

  17. Check if string is 'inside' an enum

    By ljepson74,   
    • 4 replies
    • 4.4k views

  18. Determining change in signals

    By Nimesh,   
    • 1 reply
    • 2.7k views

  19. Use of wait statement

    By Nimesh,   
    • 2 replies
    • 4.1k views

  20. Transaction Logging

    By Nimesh,   
    • 1 reply
    • 1.5k views

  21. Covergroup instance issue - system verilog coverage

    By smitgovani,
    • 1 reply
    • 2k views

  22. UVM_WARNING to stop simulation

    By bjoernohlau,
    • 3 replies
    • 936 views

  23. OSPI Register Model (unmapped register and non-register access)

    By Henry,
    • 4 replies
    • 1.2k views

  24. uvm_field_macros

    By kapil705,   
    • 1 reply
    • 1.9k views

  25. UVM RAL uvm_mem 8 bits wide memories mapped into map with 32 bits word

    By KristinaD,   
    • 0 replies
    • 872 views
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