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ljepson74

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ljepson74 last won the day on December 1 2015

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  1. How can I write the following sequence? If sequence A happens, then sequence A may not happen again until either sequence B or sequence C happens. An example of the sequences might be: sequence seqA; ($rose(A)) ##1 $fell(A); //single cycle A pulse endsequence sequence seqB; B[->1]; //B high for 1 cycle endsequence sequence seqC; (1[*10]); //10 clk cylces endsequence It is important in this question that seqA is a sequence, so that we are not just checking seqA |-> (!A throughout (seqB or seqC)) (For this simple example, afte
  2. Thanks, David. Your response got me reading about the quality of RNGs (which was nice, but not my goal) and your initial example was in C. I was just looking for a way to make a simple system call (from SystemVerilog) to set the seed; to run a handful of times in succession with different seeds. I didn’t read far enough into Doug’s paper**1 to see his example code that you used in your most recent example. % head -4 /dev/urandom | od -N 4 -D -A n | awk '{print $1}' Your second example, www.edaplayground.com/x/Zve, is what I was looking for. Thank you. I use it as you suggeste
  3. basarts, Good point. I had looked into “expr” and some other commands besides date, but should have been looking at exit codes. (I must have been looking at various SV procedures that can be called as either tasks or functions, for too long.) It seems any solution for my original question would require some external, non-SystemVerilog code and a DPI or similar call, which I’ll avoid for my current study purposes on edaplayground. Thanks.
  4. Can a distribution value_range be a list? Or is there way to achieve the same result using "dist"? As shown by non-working example code, I try to do something like this: bit [1:0] twobits; assert(std::randomize(twobits) with {twobits dist {2'b10:=50, inside{2'b00,2'b11,2'b01;}:/50};} ); //INCORRECT assert(std::randomize(twobits) with {twobits dist {2'b10:=50, [2'b00,2'b11,2'b01]:/50};} ); //INCORRECT "18.5.4 Distribution" image snippet from IEEE_Std1800-2017 LRM attached. Is there (isn't there) a way that value_range can be a list of choices, which
  5. Thanks a lot, David. My objective here is simply to be able to push "Run" on edaplayground a few times (usually <5), and to see different results. On Questa, I can use "-svseed=random". I don't know the settings for all of the simulators, so tried an experiment to generate random seeds 100% from within SystemVerilog, as I wrote above (rather than using compiler/simulator switches). For my purposes, if the randomess is not very good ... I don't care. The quality of the randomness is not my objective here. Thanks for that detailed reply, however. You and Doug are great teachers. I'
  6. Does $system() really return an int when called as a function? (Perhaps no one has implemented this part of the LRM?) int myseed; myseed = $system("date"); //should output "return value of the call to system() with data type int" quote source: IEEE_Std1800-2017 Section 20.18.1 $system I have not been able to get a non-0 return value, as far as I can tell. Am I doing something incorretly or is this not implemented? What if $system("date") is called? I suppose the "date" system output is longer than 32b, so perhaps the lowest bits are all 0s and the upper ones that c
  7. @kurtlin , do you know this by chance? I am looking for each VCS simulation 'run' to use a different seed. (I'm using EDAPlayground, so don't have access to a set of user guides.) On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below. (I suspect that -sv=2009 is a superset of "-assert svaext". So, I'll probably stick with that. Thanks again.) Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date") **1:
  8. Yes, thanks Dave. (I saw that. I was trying not to make comparisons between them, lest I violate some benchmarking rule or such.) (I'll move on to another topic now, as I work to get the rust off of my SystemVerilog skills.)
  9. Thank you. I could not (easily, so I gave up) find information about the compiler switches online. a) -sv=2009 works and the compiler error disappears b) The assertion AS_TRUE5_STRONG does not fail, as expected, based on the LRM description of "strong". IEEE_Std1800-2017 : 16.12.2 Sequence property Aren't the clock cycles of the sequence which do not complete (because the simulation ends) empty matches?
  10. The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a[19]; always clk = #5 ~clk; always
  11. Does VCS 2019.06 support strong and weak? (Or is there a VCS switch needed to use LRM 2009+?) I get the following error with the code below. Error-[IND] Identifier not declared testbench.sv, 15 Identifier 'weak' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Error-[IND] Identifier not declared testbench.sv, 16 Identifier 'strong' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Code: //Weak & Strong seem to not work in VCS 20
  12. Synopsys VCS: What is the run option to use a random seed?
  13. mastrick, Thanks for that. That is a very good point. For forums or any sort of Q&A I try to show the focus of the post as succinctly as possible. Doing so, I sometimes use styles I wouldn't ordinarily, like skipping a "begin ... end" when it is not required because there is only one line of code. (I like to always use begin/end and heavily use parentheses to be explicit.) I agree with your point. Why am I responding to threads from 4 years ago, one might ask? Because after 3 years of not using UVM and almost no SystemVerilog, I am trying to get the rust off
  14. Note: There will be a reply coming soon by user “jdickol”. (He recently registered, so his reply likely needs moderator approval, but he messaged me directly.) Thanks for the solution, jdickol. This is how the constraint can be written: constraint total_weight { (animal_da.sum with (item.weight)) == 100; } Output: # animal weight:39 # animal weight:24 # animal weight:37 # ***********************Total weight: 100 # animal weight: 7 # animal weight:36 # animal weight:57 # ***********************Total weight: 100 # animal weight:48 # animal weight:28 # anima
  15. I've simplified the example. Goal: Using constraints in group_of_animals_c, can we constrain the sum of the animal weights? I'd prefer to avoid procedural code in functions being called. My goal is understand if/how a constraint might reach thru class handles and affect properties in the objects contained by the object which is being randomized. //Class animal_c has a property "weight". //For an array of animal_c (as part of class group_of_animals_c), // the total weight of the animals should be 100. //How can this be done with constraints? //Can a constraint expression refe
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