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ljepson74 last won the day on December 1 2015

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  1. I nudge this comment to get some more eyes on it, as SystemVerilog folks may now be thinking about the next version of the LRM.
  2. Note/Clarification: With VCS 2019.06 and Riviera Pro 2020.04, the code in the original post works as I expected. cg_fa[0] - Coverage=78.12 % cg_fa[1] - Coverage=1.56 % I try to write code which has "universal" support across "all" simulators. Is the difference across simulators due to ambiguity in the LRM? Is some aspect of my code using a poor style? How can this code be improved for more universal simulator support? (I am trying to avoid publically contrasting simulators, which afaik is verboten.)
  3. Using an array of class objects which have a covergroup in them, I've run into the following problems. I look for a solution which is supported by all/most simulators. This topic array seems to be a common issue, based upon web search results. ERROR TYPE0: Same coverage is recorded for both covergroups, despite option.per_instance=1 being used. # vsim -voptargs=+acc=npr # cg_fa[0] - Coverage=81.25 % # cg_fa[1] - Coverage=81.25 % ERROR TYPE1: Compile error with another simulator cg_fa[0] - Coverage=xmsim: *N,COVNSM: (File: ./testbench.sv, Line: 42):(Time: 0 FS + 0) Sampling of covergroup type "cg_wrapper::cg" (./testbench.sv:7), referred in the statement is not enabled. As a result, coverage methods get_coverage(), get_inst_coverage(), get_hitcount(), and get_inst_hitcount() will return 0 coverage. Relevant LRM reference: IEEE_Std1800-2017 19.8.1 Overriding the built-in sample method Code: https://edaplayground.com/x/6Zuh Does anyone have a tip for either of these issues? package data_types_pkg; class cg_wrapper; covergroup cg with function sample ( bit [7:0] data ); option.per_instance = 1; cp_data : coverpoint data[7:0]; endgroup : cg function new(); cg = new(); endfunction endclass : cg_wrapper endpackage : data_types_pkg // MODULE: TOP // The testbench of covergroup array module top; import data_types_pkg::*; cg_wrapper cg_fa[2]; initial begin $display("Make cg_fa[0]"); cg_fa[0] = new(); //supply transaction as ref to covergroup instances instances cg_fa[0].cg.set_inst_name("cg_fa[0]"); $display("Make cg_fa[1]"); cg_fa[1] = new(); //supply transaction as ref to covergroup instances instances cg_fa[1].cg.set_inst_name("cg_fa[1]"); //Sample each, but mainly [0] repeat (100) begin // many samples for [0] cg_fa[0].cg.sample( $urandom()%256 ); // //#5; // TRIED TO ADD DELAY SO DIFFERENT TIME SLOTS USED end // ALSO TRIED TO CALL SAMPLE() from automatic function repeat ( 1) begin // few samples for [1] cg_fa[1].cg.sample( $urandom()%256 ); // //#5; end //Report coverage $display ("cg_fa[0] - Coverage=%0.2f %%", cg_fa[0].cg.get_inst_coverage()); $display ("cg_fa[1] - Coverage=%0.2f %%", cg_fa[1].cg.get_inst_coverage()); end endmodule As a side-note/question: If a simulator does not allow access to a covergroup's name with "cg.option.name" access (i.e. dot notation, such as to print it), then if name string is set with set_inst_name, how else can it be accessed? Only in a tool output report?
  4. How can I write the following sequence? If sequence A happens, then sequence A may not happen again until either sequence B or sequence C happens. An example of the sequences might be: sequence seqA; ($rose(A)) ##1 $fell(A); //single cycle A pulse endsequence sequence seqB; B[->1]; //B high for 1 cycle endsequence sequence seqC; (1[*10]); //10 clk cylces endsequence It is important in this question that seqA is a sequence, so that we are not just checking seqA |-> (!A throughout (seqB or seqC)) (For this simple example, after seqA, perhaps a 2 cycle pulse of A is acceptable, before seqB or seqC. So we specifically check for a 1 cycle pulse of A.) Although some auxiliary/extra code outside of the sequences and property (perhaps a small state machine) might help, I attempt to avoid extra code, to better understand SVA. One of my many failed attempts involves something like a liveness property. Is this a correct/possible approach? sequence seqA_with_buffer; (##[0:$] seqA ##1 1[*]); endsequence seqA |-> ( (not seqA_with_buffer) ##0 seqB ##0 seqC ) //edit: Now that I look at this again (after posting), I don't think the buffer is needed ... if this could be made to work Some non-working code is here: https://edaplayground.com/x/5z5n
  5. Thanks, David. Your response got me reading about the quality of RNGs (which was nice, but not my goal) and your initial example was in C. I was just looking for a way to make a simple system call (from SystemVerilog) to set the seed; to run a handful of times in succession with different seeds. I didn’t read far enough into Doug’s paper**1 to see his example code that you used in your most recent example. % head -4 /dev/urandom | od -N 4 -D -A n | awk '{print $1}' Your second example, www.edaplayground.com/x/Zve, is what I was looking for. Thank you. I use it as you suggested, and now can set the seed without needing to know the simulator options to use a random seed. **1 https://www.doulos.com/media/1293/snug2013_sv_random_stability_paper.pdf
  6. basarts, Good point. I had looked into “expr” and some other commands besides date, but should have been looking at exit codes. (I must have been looking at various SV procedures that can be called as either tasks or functions, for too long.) It seems any solution for my original question would require some external, non-SystemVerilog code and a DPI or similar call, which I’ll avoid for my current study purposes on edaplayground. Thanks.
  7. Can a distribution value_range be a list? Or is there way to achieve the same result using "dist"? As shown by non-working example code, I try to do something like this: bit [1:0] twobits; assert(std::randomize(twobits) with {twobits dist {2'b10:=50, inside{2'b00,2'b11,2'b01;}:/50};} ); //INCORRECT assert(std::randomize(twobits) with {twobits dist {2'b10:=50, [2'b00,2'b11,2'b01]:/50};} ); //INCORRECT "18.5.4 Distribution" image snippet from IEEE_Std1800-2017 LRM attached. Is there (isn't there) a way that value_range can be a list of choices, which are not in a range? For example 00, 11, 01. I thought I had done this in the past, but now, a few years out of the SV game, I can't seem to get it to work. I can think of other ways to (Maybe an array holding the values, or something like that? Perhaps I simply imagine that I ever did this using a dist.)
  8. Thanks a lot, David. My objective here is simply to be able to push "Run" on edaplayground a few times (usually <5), and to see different results. On Questa, I can use "-svseed=random". I don't know the settings for all of the simulators, so tried an experiment to generate random seeds 100% from within SystemVerilog, as I wrote above (rather than using compiler/simulator switches). For my purposes, if the randomess is not very good ... I don't care. The quality of the randomness is not my objective here. Thanks for that detailed reply, however. You and Doug are great teachers. I've been in very helpful Doulos classes with both of you. I'll minimize my questions to these: 1) Can anyone get SystemVerilog's $system() function to return anything besides 0? I have not been able to. Is it not implemented or am I doing something incorrectly? 2) What switches will provide random seeds for Aldec Riviera and Synopsys VCS?
  9. Does $system() really return an int when called as a function? (Perhaps no one has implemented this part of the LRM?) int myseed; myseed = $system("date"); //should output "return value of the call to system() with data type int" quote source: IEEE_Std1800-2017 Section 20.18.1 $system I have not been able to get a non-0 return value, as far as I can tell. Am I doing something incorretly or is this not implemented? What if $system("date") is called? I suppose the "date" system output is longer than 32b, so perhaps the lowest bits are all 0s and the upper ones that contain the date are truncated. ? Some sample code: https://edaplayground.com/x/4dw6 ==================================================================== Ultimate Objective: Use $system("date") to set the seed using $srandom(). Reason: I haven't easily found the simulator run switches for the different simulators to use random seeds for each run. So, I try to make universal SystemVerilog code (just for use on edaplayground with small examples), to use a random seed for each run, based on the wall clock time. //Compiler / simulator run switches to set random seed in SystemVerilog simulators Aldec Riviera: ? ? ? Cadence Xcelium: -seed random Mentor Questa: -svseed=random Synopsys VCS: ? ? ? (I feel comfortable posting this, as I don't consider this any form of benchmarking between simulators, but just equating compile options.)
  10. @kurtlin , do you know this by chance? I am looking for each VCS simulation 'run' to use a different seed. (I'm using EDAPlayground, so don't have access to a set of user guides.) On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below. (I suspect that -sv=2009 is a superset of "-assert svaext". So, I'll probably stick with that. Thanks again.) Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date") **1:
  11. Yes, thanks Dave. (I saw that. I was trying not to make comparisons between them, lest I violate some benchmarking rule or such.) (I'll move on to another topic now, as I work to get the rust off of my SystemVerilog skills.)
  12. Thank you. I could not (easily, so I gave up) find information about the compiler switches online. a) -sv=2009 works and the compiler error disappears b) The assertion AS_TRUE5_STRONG does not fail, as expected, based on the LRM description of "strong". IEEE_Std1800-2017 : 16.12.2 Sequence property Aren't the clock cycles of the sequence which do not complete (because the simulation ends) empty matches?
  13. The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a[19]; always clk = #5 ~clk; always@(posedge clk) begin gnt_a = gnt_a<<1; $display($time," gnt: %1b",gnt); end as_v1 : assert property ( @(posedge clk) not strong(gnt[*2]) ); as_v2 : assert property ( @(posedge clk) gnt |-> ##1 !gnt ); as_v3 : assert property ( @(posedge clk) gnt ##1 1'b1 |-> !gnt ); endmodule Code is also available here: https://edaplayground.com/x/4GXn
  14. Does VCS 2019.06 support strong and weak? (Or is there a VCS switch needed to use LRM 2009+?) I get the following error with the code below. Error-[IND] Identifier not declared testbench.sv, 15 Identifier 'weak' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Error-[IND] Identifier not declared testbench.sv, 16 Identifier 'strong' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none. Code: //Weak & Strong seem to not work in VCS 2019.06 module top; bit clk; initial begin #100; $finish; end always clk=#5~clk; AS_TRUE5 : assert property (@(posedge clk) (1[*5]) ); //per 2009+ LRM, this should be weak by default, so pass AS_TRUE5_WEAK : assert property (@(posedge clk) weak (1[*5]) ); //per 2009+ LRM, this should pass AS_TRUE5_STRONG : assert property (@(posedge clk) strong (1[*5]) ); //per 2009+ LRM, this should fail **1 //**1: Should fail because at end of sim, there will be one or more start cycles, which were not the start of five cycles (because sim ends). So for those, the seq does not complete endmodule https://edaplayground.com/x/29PM
  15. Synopsys VCS: What is the run option to use a random seed?
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