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Showing results for tags 'ral'.
Found 15 results
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I am trying to verify 8 bit RW registers and in some of the registers 4 bits are RESERVED lets say [3:0] . My bit bash sequence tries to write in these constant bit and flags me a mismatch error in the DUT and Mirrored Value. How do i stop my bit bash sequence from checking these RESERVED bits of a register. Thanks for your help -
Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina -
Hello, I was wondering if are there any resources (papers, blogs, posts, best practices) about methodologies to implement UVM RAL for "large" designs (>100K registers and 50K rams)? I tried to do some research online but most of the results never cover "large" designs. I have experience using RAL and doing some customisation to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were "little" (1K regs and 100 rams) I'm interested on any information about aspects such as: Reg model re-usability and portab -
Hi, I have an issue where teh DUT returns an X for register read but the reg2bus still sees it as a 0. When I was going over the uvm_reg_bus_op struct the type for data is uvm_reg_data_t which is only 2-state. Is there a way to override this argument to support 3/4-state? Maybe uvm_reg_data_logic_t? Please let me know. Thanks in advance! Vignesh -
I recently came upon an issue where attempting to write a memory via a backdoor yields a warning similar to the following: "reporter [RegModel] Memory 'tst_reg_blk.test_mem' is not contained within map 'Backdoor' (called from get_access())" In addition to the warning, it appears that due rw.map being overwritten (as explained in the second link), Read-Only memories can be written to via the backdoor, since get_access end up returning the default value of "RW". This appears to be in conflict with the Spec: Researching this warning turned up a couple prior forum posts from 201 -
Hi All, I am working in verification. Where i have to generate reg_block for all the IP's using IPXACT. also top level reg_block which instantiates all the IP level register block using IPXACT. But i am not interested in Ports/Businterface/component. Please advise me what is the best method to do it. Thanks Saravanan
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The VCS implementation of uvm_reg_bit_bash_seq UVM register bit bash sequence performs a model.reset() in the sequence body, before starting the core do_block() task. Due to this reset, any configurations made to the DUT before starting the bit bash sequence is lost in the mirror model, while the DUT still has the configuration intact. This is causing failures during the bit-bash process, resulting in a test fail. There is no knob to override the reset functionality, nor can I extend the sequence and bypass the reset. Any thoughts on this? Any work around for this? ~C -
Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows: reg_model.default_map.set_sequencer(spi_master_agt.mem_sqr, reg2spi_adapter); The transaction type handled by the spi_master_agt.mem_sqr is spi_mem_tr. Now I need to extend the spi_mem_tr to spi_mem_tr_1 and spi_mem_tr_2, and then override spi_mem_tr with those separately for the 2 objects of the SPI env class. // Below does not work set_inst_override_by_type ( .relative_inst_path("env.spi_m[0].*"), // Here spi_m[0] is the fi -
Looking for suggestions on the best approach to modeling something akin the following. value1 and value0 are implemented as value_reg[31:0] in RTL. The value actually stored in this register is always whatever you wrote to it. However, what you read back, and what HW sees when it looks at this register depends on the value of value_mode. When value_mode == DIRECT, you'll read back the whatever value is physically stored in value_reg[15:0] as value0 and value_reg[31:16] as value1. When value_mode == MULT, you'll read back a computed value instead. Let quotient == value_reg[15:0 -
Hi, We are using snps ralgen to generate the regmodel. It appears that the ralgen creates only the default map. We would like to have 2 maps for 2 separated if masters. Is there an online example for such case? A post gen script can do one of the following 2 options: 1. add another instance of uvm_reg_map and copy/clone the ready map after finished build 2. add another instance of uvm_reg_map, and duplicate any map1.add_reg and map1.add_submap to map2 Which is preferable? Thanks! Elihai
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Hi, I have a question refer to strange messages created by RAL read command. When the register is read, I receive a message like: uvm_pkg::uvm_parent_child_link l103=config_dmaw_seq r107=transfer Do you know how to prevent these messages? Regards, Moshe
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Hello all, Sorry for stupid question. I have my registers defined as, reg1, reg2, reg3.....................reg64. Now i want to drive a single value (ZERO) to all register using for loop. so i implemented, for (integer i = 0; i<65; i = i+1); des_data[0:7] = 8'h00; block_obj.$sformatf("reg%0d",i).write(status, des_data, UVM_FRONTDOOR,.parent(this)); But i am unable to achieve so. Any one else can suggest alternate solution or logic for the above problem ??
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Hi, I wanted to use the field.mirror() task provided in the uvm_reg_field class to check only a particular field. However, I see that the field.mirror() task is just calling the parent register mirror task. Hence the entire register is read and compared which I didn't intend to do. I tried this in my sequence and I see the above mentioned behavior. This looks like a serious bug. Can you please confirm this. Regards, Shreyas -
Hello All, I have some queries regarding RAL model : (1.) How to declare any particular Register's filed as "signed" in RAL model? (2.) By default all the register fields in RAL model are "unsigned" or "signed"? If possible please guide me for the same. Thanks, Bonny G. Vora
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Not sure do you have similar problem? I have a problem in handling the reset value in RAL. f the reset value of a field in the register is don't care, what can I do for it? Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked. Do you guys think it is a feasible way? Thanks.
