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Verilog bug issue


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module de_3_to_8( in,decoder_out,enable);
  input [3:0] in;
  output [7:0] decoder_out;// syntax error

  //individual wires
  assign decoder_out[0]= ~in[2] & ~in[1] & ~in[0];
  assign decoder_out[1]= ~in[2] & ~in[1] & in[0];
  assign decoder_out[2]= ~in[2] & in[1] & ~in[0]; 
  assign decoder_out[3]= ~in[2] & in[1] & in[0];
  assign decoder_out[4]= in[2] & ~in[1] & ~in[0];
  assign decoder_out[5]= in[2] & ~in[1] &  in[0];
  assign decoder_out[6]= in[2] &  in[1] & ~in[0];
  assign decoder_out[7]= in[2] &  in[1] &  in[0];


Error: At line 3 syntax error. I`m not knowing what is the error with the syntax.




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