Verilog bug issue

[Tarzan]

module de_3_to_8( in,decoder_out,enable);
  input [3:0] in;
  output [7:0] decoder_out;// syntax error

  //individual wires
  assign decoder_out[0]= ~in[2] & ~in[1] & ~in[0];
  assign decoder_out[1]= ~in[2] & ~in[1] & in[0];
  assign decoder_out[2]= ~in[2] & in[1] & ~in[0]; 
  assign decoder_out[3]= ~in[2] & in[1] & in[0];
  assign decoder_out[4]= in[2] & ~in[1] & ~in[0];
  assign decoder_out[5]= in[2] & ~in[1] &  in[0];
  assign decoder_out[6]= in[2] &  in[1] & ~in[0];
  assign decoder_out[7]= in[2] &  in[1] &  in[0];
 
endmodule

 

Error: At line 3 syntax error. I`m not knowing what is the error with the syntax.

 

Regards

Devesh

[chr_sue]

You have to specify the data direction for the enable port.

[Tarzan]

Thank you sue. I have got this code working at present but I`m trying to analyze the output of this at the moment in which I have been having few doubts. After this I will update you accordingly.