Use of wait statement

[Nimesh]

I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in  displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this :

@(negedge clk)

wait(rdata)

$fdisplay(rdata)

But there could be multiple non-zero Read transactions. Now i am stuck here :

@(negedge clk)

//wait for rdata to change

$fdisplay(rdata)

I am new to verilog and SystemVerilog. Please help

Thank you 

[David Black]

This is not really a UVM topic and should be posted under a SystemVerilog or Verilog forum. Sounds like you could use basic SystemVerilog training.

You might be served by a simple:

initial begin
  $monitor( $time,,wdata,,rdata ); ///< Display wdata or rdata anytime they change
end

There can only be one $monitor active at any time. So if you have more than one need, you have to combine all into a single monitor.

At any rate, perhaps you could put a code sample illustrating the problem on www.EDAplayground.com then share the link back here.

[Nimesh]

I have to not only display but write the values in a file also. I am unable to figure when to write it to the file.

 

I am attaching a picture for the scenario. The rdata is a 32-bit value and not a single.Shown for simplicity as a single bit. See how the rdata changes between two clock pulses. How can i record that data