Nimesh Posted June 12, 2020 Report Share Posted June 12, 2020 I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata to change $fdisplay(rdata) I am new to verilog and SystemVerilog. Please help Thank you Quote Link to comment Share on other sites More sharing options...
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