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chr_sue

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chr_sue last won the day on May 14

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  1. You have to specify the data direction for the enable port.
  2. Could you please explain what you mean saying 'verify register file content through assertion'. What is 'register file content'? Assertions are used to verify dynamic behavior. What you are sayying sounds static.
  3. These terms are different. A virtual sequence defines how the local/agent sequences should behave. A virtual sequence contains sequences of different types/inheritence. The sequence library allows you to add sequences of the same type/inheritence to it. Then you can start the sequence library like a single sequence and all the sequences belonging to it will be executed in a certaim order, defind by the specified execution mechanism.
  4. You have a few weaknesses in your code: (1) Your class seq seems to be a virtual sequence, because you do not parameterize it for a ceratin seq_item. In the body task you are creating seq_items. (2) You are declaring vsqr as p_sequencer and at thge same time you are using it as virtual sequencer. (3) If you do not have a forever loop in your sequence it comes always to its end. It is useless to stop sequences with the corresponding commands. (4) run_test instantiates your test implicitly You do not have to construct it explicitely. (5) sequences are transient objects
  5. You do not say anything about a relationship between interface A and B, i.e. can you do a few transactions on the cmd interface without needing the data from the data interface or vice versa. Please elaborate.
  6. Make it easy. Do a type cast to string. See below the code: module top; typedef enum {alpha, beta, gamma, delta, epsilon} my_enum; string my_string; my_enum state; initial begin state = beta; my_string = string'(state.name); $display("string = %s", my_string); end endmodule
  7. Please look here at Using UVM_LOG in https://verificationacademy.com/cookbook/messaging/usingmessaging
  8. You dot need a reference to the covergroup class. You can omit this line of code: cg_fsm_state cg_fsm_state_inst; In the constructor you are calling new directly on the coverage class name: cg_fsm_state = new();
  9. If you do not know from which piece of code this message comes set a reasonable timeout in the toplevel module of your UVM testbench.
  10. I believe the problem comes from here. The UVM Reference Manual says: If unmapped is True, the register does not occupy any physical addresses and the base address is ignored. Unmapped registers require a user-defined front door to be specified. The default value of unmapped shall be 0, which is FALSE. Because there is no physical address for this type of registers it will not be updated.
  11. I found an example on the Doulos webpage. The code is in the EDAPlayground: https://www.edaplayground.com/x/4vf Hope this helps.
  12. I believe you have a wrong understanding of the UVM RAL. A few aspects only: (1) the frontdoor sequence you are mentioning is not frontdoor/backdoor. It is a specific class to define a complex sequence related behavior. See the UVM Ref.Manual for the details. (2) the OSPI sequence does not go through the adapter using reg2bus and bus2reg. (3) The adapter is used to convert a generic UVM RAL sequence into a OSPI sequence. (4) Each register sequences has to have a specific access type like RO, RW etc. This might be a few ideas to work on your issue.
  13. The register adapter contains 2 functions: (1) bus2reg (2) reg2bus bus2reg implements the path from the pinlevel interface to the register layer. This is the path which returns the rD-data (ahb_hrdata). reg2bus implements the path from the register layer to the pimlevel interface. This is the path which is used to send the WR-data ahb_hwdata) from the register layer to the DUT.
  14. Unfortunately you do not show a piece of code. But the 3rd argument has to be a bit type (1'b1 for replacing).
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