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Covergroup instance issue - system verilog coverage


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Hi,

I am trying to take instance of covergroup but unable to take it. Getting compilation instance.

class model extends uvm_component;

`uvm_component_utils(model)

bit [2:0] state;

 covergroup cg_fsm_state;

  c1 : coverpoint state;

endgroup

cg_fsm_state cg_fsm_state_inst;

function new();

cg_fsm_state_inst = new();

endfunctiion 

endclass

 

Using above code, getting compilation error as mentioned below 

Error-[SE] Syntax error
  Following verilog source has syntax error :
      token 'cg_fsm_state' should be a valid type. Please declare it
  virtual if it is an Interface.
  "/vobs/cores/infrastructure/cia_resourcecontrol/aon_mod_verif/sim/models/./aon_mod_fsm_ref_model.sv",
  208: token is ';'
    cg_fsm_state  cg_fsm_state_inst;
 
Regards,
Smit
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