Jump to content

Recommended Posts

Posted

I am working on a large project with multiple Verilog/SystemVerilog config-endconfig files. Many of the config files have the statement:

   default liblist gates_lib work;


I understand "default liblist" and the "gates_lib." I have not previously seen the "work" library at the end of the default liblist statement.

Can someone explain what this is used for? I don't think there are any libraries specifically defined for "work." This looks like it might be related to separate compilation.

The IEEE 1800-2017 Standard does not show any examples with the added "work" library.

I am just trying to figure out if I really need the "work" portion of this liblist statement (very large project so it is tricky to hunt down all of the dependencies).

Regards - Cliff Cummings

Posted

We are not using Questa on this project, so the question is, do I really need to specify the work library? I am thinking that there may be some separate-compilation reason to add or exclude it.

I actually helped get configurations into the Verilog-2001 Standard, so as mentioned before:

The IEEE 1800-2017 Standard does not show any examples with the added "work" library. Why would I need it?

Regards - Cliff

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...