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Showing results for tags 'uvm_sequence'.
Found 4 results
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What is the difference between "uvm sequence library" and "virtual sequence" ? Are these same in usage or different ?
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I've been using various types of calling uvm_sequences while developing sequences and every approach works. But I've a doubt what is the best one to be used when compared between using uvm_create, uvm_send and start_item, finish_item. In either cases the type and amount of control on the transactions is the same. Can anyone help me in understanding the differences better? Are there any guidelines to choose a specific style of coding for a given requirement? Thanks -
Hi there We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address. We have the following pseudocode: model.NTB_DB.get_registers(total_regs_ntb); foreach (total_regs_ntb) begin total_regs_btb.write(status, wdata, .parent(this)); end But, the above source code does not go through the registers space based on address. ie., When I have a 2-dimensional array of registers, array indices are chosen first(not addresses). Any help to workaround this problem is appreciated. Best regards Balasubramanian G -
Hi all, How to pass the value to the variable of uvm_sequence object? 1. use uvm_config_db 2. assign directly When i use the first way, i found that maybe uvm_config_db::get() can only use in the uvm_component class. Then i use the second way, I cann't pass the value to the variable successfully. Does anybody know the reason? Thanks in advance. pieces of code of the first way: In top: uvm_config_db#(uvm_bitstream_t)::set(uvm_root::get(), "*", "my_cpu_id", HOST_NUM); In my_sub_sequence which extends from uvm_sequence: void'(uvm_config_db#(uvm_bitstream_t)::get(this, "", "my_c
