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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. UVM 1.2 report_summarize()

    By Andrew,   
    • 0 replies
    • 2.1k views

  2. randomize(argument) checks all constraints in scope

    By ljepson74,   
    • 3 replies
    • 4.7k views

  3. uvm_event with uvm1.2

    By Parth1242,
    • 3 replies
    • 2.1k views

  4. FORK JOIN_NONE in UVM_SEQUENCE

    By karandeep963,
    • 2 replies
    • 2.2k views

  5. UVM_ERROR

    By Prawin,
    • 0 replies
    • 1.1k views

  6. Using parametrized class in package

    By soloist_huaxin,
    • 2 replies
    • 1.4k views

  7. UVM report_phase not being executed

    By Joe Twwedie,   
    • 3 replies
    • 1.9k views

  8. Uvm

    By Shobhana soni,
    • 0 replies
    • 917 views

  9. Uvm

    By Shobhana soni,
    • 0 replies
    • 667 views

  10. Read only behavior for uvm_transaction classes used to create verification component configuration object

    By udmittal,
    • 1 reply
    • 1.1k views

  11. Constraints

    By Shobhana soni,   
    • 2 replies
    • 2.6k views

  12. Randomization in an initial block

    By gbbrown,
    • 2 replies
    • 6.4k views

  13. UVM Override V/s Simulator Compile/Elab

    By karandeep963,   
    • 2 replies
    • 1.2k views

  14. Accessing memory model from different components in the design

    By cooltoad,   
    • 0 replies
    • 1.1k views

  15. Question about connecting two uvm_tlm_nb_passthrough_initiator_socket

    By tjwang0709,
    • 0 replies
    • 857 views

  16. Creating the right sequence item structure in UVM

    By Bravo,   
    • 0 replies
    • 1.5k views

  17. How to get the value of a string when using the string in a hierarchical path

    By jcvobu,
    • 2 replies
    • 4.5k views

  18. starting phase in default sequence

    By Shankar`,
    • 1 reply
    • 7.1k views

  19. Difference between Master and Slave Agents

    By Shankhadeep,
    • 1 reply
    • 5.6k views

  20. Significance of type_id

    By Parivesh Gupta,
    • 2 replies
    • 5.4k views

  21. is the behaviour of phase.find_by_name intentional?

    By justrajdeep,   
    • 0 replies
    • 965 views

  22. block level verification in a system setting

    By c4brian,   
    • 5 replies
    • 3.2k views

  23. Sequencer Not Supplied to Start Item in Sequence

    By astod,
    • 1 reply
    • 7.8k views

  24. interface must be assigned a matching interface or virtual interface

    By ssingh,
    • 3 replies
    • 5.7k views

  25. Where to create regmodel? ...in the test or the env?

    By mooredan,
    • 3 replies
    • 3.7k views
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