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Using an array of class objects which have a covergroup in them, I've run into the following problems. I look for a solution which is supported by all/most simulators. This topic array seems to be a common issue, based upon web search results. ERROR TYPE0: Same coverage is recorded for both covergroups, despite option.per_instance=1 being used. # vsim -voptargs=+acc=npr # cg_fa - Coverage=81.25 % # cg_fa - Coverage=81.25 % ERROR TYPE1: Compile error with another simulator cg_fa - Coverage=xmsim: *N,COVNSM: (File: ./testbench.sv, Line: 42):(Time: 0 FS + 0) Sampling of covergroup type "cg_wrapper::cg" (./testbench.sv:7), referred in the statement is not enabled. As a result, coverage methods get_coverage(), get_inst_coverage(), get_hitcount(), and get_inst_hitcount() will return 0 coverage. Relevant LRM reference: IEEE_Std1800-2017 19.8.1 Overriding the built-in sample method Code: https://edaplayground.com/x/6Zuh Does anyone have a tip for either of these issues? package data_types_pkg; class cg_wrapper; covergroup cg with function sample ( bit [7:0] data ); option.per_instance = 1; cp_data : coverpoint data[7:0]; endgroup : cg function new(); cg = new(); endfunction endclass : cg_wrapper endpackage : data_types_pkg // MODULE: TOP // The testbench of covergroup array module top; import data_types_pkg::*; cg_wrapper cg_fa; initial begin $display("Make cg_fa"); cg_fa = new(); //supply transaction as ref to covergroup instances instances cg_fa.cg.set_inst_name("cg_fa"); $display("Make cg_fa"); cg_fa = new(); //supply transaction as ref to covergroup instances instances cg_fa.cg.set_inst_name("cg_fa"); //Sample each, but mainly  repeat (100) begin // many samples for  cg_fa.cg.sample( $urandom()%256 ); // //#5; // TRIED TO ADD DELAY SO DIFFERENT TIME SLOTS USED end // ALSO TRIED TO CALL SAMPLE() from automatic function repeat ( 1) begin // few samples for  cg_fa.cg.sample( $urandom()%256 ); // //#5; end //Report coverage $display ("cg_fa - Coverage=%0.2f %%", cg_fa.cg.get_inst_coverage()); $display ("cg_fa - Coverage=%0.2f %%", cg_fa.cg.get_inst_coverage()); end endmodule As a side-note/question: If a simulator does not allow access to a covergroup's name with "cg.option.name" access (i.e. dot notation, such as to print it), then if name string is set with set_inst_name, how else can it be accessed? Only in a tool output report?
Coverage across multiple interfaces
imajeeth posted a topic in UVM SystemVerilog DiscussionsI need to implement coverage across multiple interfaces. For example in the arbitor designs, it is of interest to see if multiple requests from different agents are driven at the same time. All the texts have only discussed coverage specific to the interface or transaction. I have an idea of implementing this, but not sure if it is the right way forward. Here is my idea: First place, instead of extending the coverage class from uvm_subscriber, I intend to extend it from uvm_scoreboard. This is because, uvm_subscriber is tied to a transaction type, whereas uvm_scoreboard is not. The code below might not be syntactically right, and I intentionally leave the factory registration, new(), build() etc. in order to be concise. `uvm_analysis_imp_decl(_transaction_A) `uvm_analysis_imp_decl(_transaction_B ) `uvm_analysis_imp_decl(_transaction_C ) class coverage_class extends uvm_scoreboard; bit req_a; //request coming from transaction A bit req_b; //request coming from transaction B bit req_c; //request coming from transaction C uvm_analysis_imp_transaction_A #(trans_a, coverage_class) trans_a_port; uvm_analysis_imp_transaction_B #(trans_b, coverage_class) trans_b_port; uvm_analysis_imp_transaction_C #(trans_c, coverage_class) trans_c_port; covergroup cg; coverpoint req_a; coverpoint req_b; coverpoint req_c; cross req_a, req_b, req_c; //Want to capture a case where all 3 requests go high at the same time from 3 different interfaces. endgroup //write function to capture trans_a virtual function void write_transaction_A(trans_a t); req_a = t.req; cg.sample(); endfunction //write function to capture trans_b virtual function void write_transaction_B(trans_b t); req_b = t.req; cg.sample(); endfunction //write function to capture trans_c virtual function void write_transaction_C(trans_c t); req_c = t.req; cg.sample(); endfunction endclass I also realize that, when 2 requests are high at the same time, there might be a delta delay between the two. Say "write_transaction_A" happens a delta before "write_transaction_B" (still the same timestamp). So when transaction_A happens, req_a is set to 1 and the covergroup is sampled. At this delta time, transaction_B has not occurred so, req_b is still 0. In the next delta cycle, write_transaction_B happens and so, req_A as well as req_B is asserted, and covergroup is sampled again. I see 2 issues here: 1. We are sampling the covergroup more than actually required. Is there a better way of sampling the covergroup? 2. Where do we clear the req_A/req_B/req_C variables in order to be sampled again. Is there a better way of accomplishing the same task? Please share your thoughts.