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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. In AXI, at what scenario can use out of order and outstanding transactions

    By Subbi Reddy Manne,   
    • 0 replies
    • 550 views

  2. How to read all the register in RAL model using reg_map?

    By nayan,
    • 2 replies
    • 5.7k views

  3. Analysis port in user callback class

    By ManMe,
    • 5 replies
    • 2.5k views

  4. Uvm ams

    By Cropty,
    • 1 reply
    • 326 views

  5. named event to trigger between class and module

    By ljepson74,   
    • 4 replies
    • 6.2k views

  6. Different registers with same register name present in different submap of register

    By asiclover,   
    • 0 replies
    • 504 views

  7. good technique to generate a random delay?

    By c4brian,
    • 11 replies
    • 27.8k views

  8. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 458 views

  9. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 591 views

  10. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 1.9k views

  11. How to create constraint for following

    By venkatasubbarao_Sutrave,   
    • 0 replies
    • 511 views

  12. sequence is not running - make sure sequencer name 'correct'

    By ljepson74,   
    • 3 replies
    • 6.1k views

  13. USB 3.0 (xHCI)

    By M s sai kamesh,
    • 1 reply
    • 396 views

  14. Confused between Definitions

    By Hany Salah,
    • 10 replies
    • 6.8k views

  15. Using get_reg_by_name() API for registers instantiated in a UVM register file

    By ankurraj,
    • 1 reply
    • 2.9k views

  16. uvm_reg_map does not clean up after itself when there's a parent sequence set

    By Georgegg,
    • 0 replies
    • 545 views

  17. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 3 replies
    • 1.5k views

  18. referencing an array of uvm_analysis_imp in a scoreboard

    By makers78,
    • 7 replies
    • 13.5k views

  19. [System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array .

    By rajivdesh,   
    • 2 replies
    • 1.8k views

  20. Base class types access through opaque type parameter extension

    By jeremyr,
    • 0 replies
    • 488 views

  21. Help needed in setting up a Hello_World UVM example project in RIVIERA-PRO 2014-10.

    By nasirkhanpak25,
    • 3 replies
    • 561 views

  22. how can we print in which phase we are in UVM

    By Serya,
    • 1 reply
    • 812 views

  23. DPI guideline for various programming language

    By Eric Hsu,   
    • 3 replies
    • 1.7k views

  24. Sft constraint vs weighted constraint

    By SV_UVM_Infant,
    • 2 replies
    • 798 views

  25. How to use a variable defined in one class into another class?

    By swapnilm,
    • 7 replies
    • 14.1k views
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