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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

598 topics in this forum

  1. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 4 replies
    • 3k views

  2. How to disable fork join or fork join_any after executed particular thread or process

    By Subbi Reddy Manne,
    • 2 replies
    • 1.3k views

  3. Interface not being loaded into config db correctly

    By LastHorizon,
    • 2 replies
    • 1.8k views

  4. Preload all the DUT

    By Peter_vertlib,
    • 0 replies
    • 403 views

  5. In AXI, at what scenario can use out of order and outstanding transactions

    By Subbi Reddy Manne,   
    • 0 replies
    • 627 views

  6. How to read all the register in RAL model using reg_map?

    By nayan,
    • 2 replies
    • 6.1k views

  7. Analysis port in user callback class

    By ManMe,
    • 5 replies
    • 2.7k views

  8. Uvm ams

    By Cropty,
    • 1 reply
    • 360 views

  9. named event to trigger between class and module

    By ljepson74,   
    • 4 replies
    • 6.4k views

  10. Different registers with same register name present in different submap of register

    By asiclover,   
    • 0 replies
    • 544 views

  11. good technique to generate a random delay?

    By c4brian,
    • 11 replies
    • 28.6k views

  12. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 505 views

  13. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 653 views

  14. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 2.1k views

  15. How to create constraint for following

    By venkatasubbarao_Sutrave,   
    • 0 replies
    • 547 views

  16. sequence is not running - make sure sequencer name 'correct'

    By ljepson74,   
    • 3 replies
    • 6.3k views

  17. USB 3.0 (xHCI)

    By M s sai kamesh,
    • 1 reply
    • 455 views

  18. Confused between Definitions

    By Hany Salah,
    • 10 replies
    • 7k views

  19. Using get_reg_by_name() API for registers instantiated in a UVM register file

    By ankurraj,
    • 1 reply
    • 3.4k views

  20. uvm_reg_map does not clean up after itself when there's a parent sequence set

    By Georgegg,
    • 0 replies
    • 600 views

  21. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 3 replies
    • 1.7k views

  22. referencing an array of uvm_analysis_imp in a scoreboard

    By makers78,
    • 7 replies
    • 13.9k views

  23. [System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array .

    By rajivdesh,   
    • 2 replies
    • 2k views

  24. Base class types access through opaque type parameter extension

    By jeremyr,
    • 0 replies
    • 568 views

  25. Help needed in setting up a Hello_World UVM example project in RIVIERA-PRO 2014-10.

    By nasirkhanpak25,
    • 3 replies
    • 604 views
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