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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

600 topics in this forum

  1. Regarding the simulation of Verilog and UVM based system Verilog files in synopsys VCS 2008.12

    By Ganesh_09,   
    • 2 replies
    • 76 views

  2. Dynamically Changing the timeout while test is running

    By Bhargav Katakam,   
    • 4 replies
    • 77 views

  3. Semantics of Verilog logical shift (<<) operator

    By chili-chips,   
    • 0 replies
    • 144 views

  4. Difference between uvm_hdl_force and uvm_hdl_deposit

    By shreyasraju,   
    • 3 replies
    • 16.9k views

  5. Is There An Existing Verification IP Core for AXI?

    By uvmstudent434,
    • 1 reply
    • 144 views

  6. UART Protocol Verification code UVM

    By Amruta A,
    • 1 reply
    • 133 views

  7. UVM RAL | Getting the Register Name

    By Revanth,
    • 1 reply
    • 565 views

  8. Bug in UVM code using byte_en?

    By jie2024,
    • 0 replies
    • 209 views

  9. constraint dist 'others'

    By ljepson74,   
    • 4 replies
    • 7.2k views

  10. Warning-[PCWM-W] Port connection width mismatch

    By Rudresh,   
    • 0 replies
    • 298 views

  11. How memory interaction between C Language in SV or UVM

    By Subbi Reddy Manne,   
    • 1 reply
    • 574 views

  12. UVM Phase Jump

    By Hany Salah,
    • 4 replies
    • 370 views

  13. Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

    By Grace90,   
    • 0 replies
    • 471 views

  14. uvm_reg_predictor possible bug when using a 64bit register with 32bit interface

    By Kamil,
    • 0 replies
    • 248 views

  15. UVM_FATAL Errors

    By Hash,
    • 10 replies
    • 18.2k views

  16. How to continue a test after getting UVM error

    By Prathyusha G,
    • 1 reply
    • 966 views

  17. How to set parameterized sequcence as default sequence with +uvm_set_default_sequence ?

    By Jaor Ma,   
    • 1 reply
    • 508 views

  18. Is the UVM write_* imp port function by default a static function?

    By liyd,
    • 2 replies
    • 508 views

  19. Is data written on register used for APB protocol

    By M Prasanth,
    • 2 replies
    • 469 views

  20. How create mutiple uvm_component instances of uvm_component array?

    By mrforever,
    • 4 replies
    • 6.9k views

  21. UVM verification... illegal assignment

    By Ravi_3,
    • 1 reply
    • 685 views

  22. Uvm factory registration disambiguation

    By bradpinn,   
    • 1 reply
    • 574 views

  23. Relationship between PSEL and PENABLE signals in the APB Protocol.

    By P.Ksagar,   
    • 1 reply
    • 687 views

  24. Argument problem of uvm_mem_region::burst_read() in uvm-1.2

    By Leon,   
    • 1 reply
    • 427 views

  25. uvm_report_object -- why only uvm_component based classed are derived from uvm_report and not uvm_sequence_item/uvm_transaction

    By dips1000,
    • 2 replies
    • 490 views
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