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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

573 topics in this forum

  1. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 31 views

  2. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 17 views

  3. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 40 views

  4. How to create constraint for following

    By venkatasubbarao_Sutrave,   
    • 0 replies
    • 28 views

  5. sequence is not running - make sure sequencer name 'correct'

    By ljepson74,   
    • 3 replies
    • 4.5k views

  6. USB 3.0 (xHCI)

    By M s sai kamesh,
    • 1 reply
    • 53 views

  7. Confused between Definitions

    By Hany Salah,
    • 10 replies
    • 5.6k views

  8. Using get_reg_by_name() API for registers instantiated in a UVM register file

    By ankurraj,
    • 1 reply
    • 180 views

  9. uvm_reg_map does not clean up after itself when there's a parent sequence set

    By Georgegg,
    • 0 replies
    • 93 views

  10. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 3 replies
    • 519 views

  11. referencing an array of uvm_analysis_imp in a scoreboard

    By makers78,
    • 7 replies
    • 10.7k views

  12. [System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array .

    By rajivdesh,   
    • 2 replies
    • 322 views

  13. Base class types access through opaque type parameter extension

    By jeremyr,
    • 0 replies
    • 133 views

  14. Help needed in setting up a Hello_World UVM example project in RIVIERA-PRO 2014-10.

    By nasirkhanpak25,
    • 3 replies
    • 140 views

  15. how can we print in which phase we are in UVM

    By Serya,
    • 1 reply
    • 183 views

  16. DPI guideline for various programming language

    By Eric Hsu,   
    • 3 replies
    • 489 views

  17. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 3 replies
    • 514 views

  18. Sft constraint vs weighted constraint

    By SV_UVM_Infant,
    • 2 replies
    • 252 views

  19. How to use a variable defined in one class into another class?

    By swapnilm,
    • 7 replies
    • 11.4k views

  20. null value when trying to get register from top reg map by get_reg_by_offset

    By Ai_Ar,   
    • 0 replies
    • 350 views

  21. How to access the instance ID of a class from a base_class, whose child class is instantiated inside.

    By Sujitha,
    • 0 replies
    • 132 views

  22. How do I get multiple transactions if register width is wider or narrower than bus width?

    By qurax,   
    • 0 replies
    • 294 views

  23. UVM randomise specific extended class only not other classes

    By Ahmad Fahad,
    • 1 reply
    • 156 views

  24. Multiple target sockets with multiple b_transport functions in one class?

    By Bas Arts,
    • 6 replies
    • 895 views

  25. any restrictions on expression in wait(expression)?

    By mastrick,
    • 6 replies
    • 9.4k views
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