UVM SystemVerilog Discussions

561 topics in this forum

1. Simulation hang due to "run_phase" not exiting

   By ankurraj, Wednesday at 08:25 AM
   • 3 replies
   • 41 views
   • 
   • tfitz
   • Wednesday at 01:02 PM

2. Sft constraint vs weighted constraint

   By SV_UVM_Infant, July 9
   • 2 replies
   • 67 views
   • 
   • SV_UVM_Infant
   • Monday at 06:34 PM

3. How to use a variable defined in one class into another class?

   By swapnilm, April 8, 2013
   • 7 replies
   • 9.9k views
   • 
   • Yuri
   • Monday at 02:23 PM

4. null value when trying to get register from top reg map by get_reg_by_offset

   By Ai_Ar, June 22   

   • register model
   • uvm
   • (and 1 more)

     Tagged with:

     • register model
     • uvm
     • adapter
   • 0 replies
   • 52 views
   • 
   • Ai_Ar
   • June 22

5. How to access the instance ID of a class from a base_class, whose child class is instantiated inside.

   By Sujitha, June 22
   • 0 replies
   • 39 views
   • 
   • Sujitha
   • June 22

6. How do I get multiple transactions if register width is wider or narrower than bus width?

   By qurax, June 12   

   • uvm
   • register model
   • (and 2 more)

     Tagged with:

     • uvm
     • register model
     • register layer
     • systemverilog
   • 0 replies
   • 64 views
   • 
   • qurax
   • June 12

7. UVM randomise specific extended class only not other classes

   By Ahmad Fahad, June 10
   • 1 reply
   • 39 views
   • 
   • dave_59
   • June 10

8. Multiple target sockets with multiple b_transport functions in one class?

   By Bas Arts, May 20, 2019
   • 6 replies
   • 617 views
   • 
   • David Black
   • June 7

9. any restrictions on expression in wait(expression)?

   By mastrick, September 26, 2012
   • 6 replies
   • 8.7k views
   • 
   • dave_59
   • June 7

10. The question on reactive slave

    By VVdemajia, September 21, 2015   

    • reactive slave AHB
    • 5 replies
    • 1.4k views
    • 
    • peegu
    • April 28

11. What happen if read access is performed on write-only register?

    By meah, April 16
    • 1 reply
    • 102 views
    • 
    • chr_sue
    • April 16

12. Hierarchical names in constant expression

    By Thomas Kruse, March 24
    • 1 reply
    • 105 views
    • 
    • dave_59
    • March 29

13. Transaction timer expired (WDT)

    By Yan, March 28
    • 5 replies
    • 92 views
    • 
    • David Black
    • March 29

14. Printer

    By bl4ckp3rl, March 25
    • 1 reply
    • 79 views
    • 
    • Mark Strickland
    • March 25

15. SystemVerilog Assertions not getting included

    By Ankit Shah, March 24
    • 2 replies
    • 73 views
    • 
    • Ankit Shah
    • March 25

16. queue/array randomize

    By shanghai1943, March 11   

    • randomize
    • 3 replies
    • 147 views
    • 
    • shanghai1943
    • March 11

17. uvm_resource_db confusion

    By shanghai1943, March 10   

    • uvm_config_db/uvm_resource_db
    • 2 replies
    • 120 views
    • 
    • David Black
    • March 10

18. field.mirror() task not working as expected

    By shreyasraju, March 7, 2014   

    • Mirror
    • RAL
    • (and 1 more)

      Tagged with:

      • Mirror
      • RAL
      • uvm_reg_field
    • 7 replies
    • 3.6k views
    • 
    • Mark Strickland
    • March 2

19. Reduction operator in case of one-bit vector

    By Thomas Kruse, February 25
    • 2 replies
    • 80 views
    • 
    • Thomas Kruse
    • February 25

20. Array of SystemVerilog Interface

    By Thomas Kruse, February 16
    • 2 replies
    • 201 views
    • 
    • Thomas Kruse
    • February 16

21. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74, May 1, 2018   

    • time slot
    • time step
    • (and 1 more)

      Tagged with:

      • time slot
      • time step
      • lrm
    • 4 replies
    • 1.6k views
    • 
    • dave_59
    • February 16

22. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K, February 13
    • 1 reply
    • 123 views
    • 
    • chr_sue
    • February 15

23. reg.randomize doesn't work for some regs

    By Weicai, February 5
    • 0 replies
    • 119 views
    • 
    • Weicai
    • February 5

24. UVM_FATAL Errors

    By Hash, January 22, 2013
    • 8 replies
    • 10.3k views
    • 
    • Gauravgos
    • February 5

25. Could not find call of check_config_usage in UVM library

    By supal, January 8
    • 2 replies
    • 137 views
    • 
    • supal
    • January 8