UVM SystemVerilog Discussions

541 topics in this forum

1. Verilog bug issue

   By Tarzan, October 29
   • 2 replies
   • 61 views
   • 
   • Tarzan
   • October 29

2. How to access register file array data using bind module

   By Dina Emadeldin, October 16
   • 1 reply
   • 55 views
   • 
   • chr_sue
   • October 21

3. Array of covergroup wrapper objects. Problems.

   By ljepson74, September 30   

   • covergroup
   • sample
   • (and 3 more)

     Tagged with:

     • covergroup
     • sample
     • override sample
     • array of covergroups
     • per_instance
   • 1 reply
   • 122 views
   • 
   • ljepson74
   • October 19

4. Consequence of not to be an "assignment-like context"

   By Thomas Kruse, October 16
   • 0 replies
   • 31 views
   • 
   • Thomas Kruse
   • October 16

5. "uvm sequence library" vs "virtual sequence"

   By Nadun, October 15   

   • uvm
   • uvm_sequence
   • (and 1 more)

     Tagged with:

     • uvm
     • uvm_sequence
     • uvm_sequence_lib
   • 1 reply
   • 46 views
   • 
   • chr_sue
   • October 15

6. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

   By DV-E, October 6
   • 2 replies
   • 55 views
   • 
   • DV-E
   • October 6

7. CAN bus verification

   By Sachin0509, September 30
   • 0 replies
   • 36 views
   • 
   • Sachin0509
   • September 30

8. $system() function return value OR Setting a random sim seed within SystemVerilog code using wallclock time.

   By ljepson74, August 29   

   • $srandom
   • $system
   • (and 4 more)

     Tagged with:

     • $srandom
     • $system
     • seed
     • random
     • compiler switch
     • system call
   • 8 replies
   • 261 views
   • 
   • David Black
   • September 14

9. SeqA |-> SeqA may not happen again before the first of SeqB or SeqC

   By ljepson74, September 11   

   • assetion
   • property
   • (and 4 more)

     Tagged with:

     • assetion
     • property
     • sequence
     • negation
     • not
     • liveness
   • 0 replies
   • 80 views
   • 
   • ljepson74
   • September 11

10. “dist”. Can a value_range be a list in a randomization distribution?

    By ljepson74, August 29   

    • dist
    • distribution
    • (and 3 more)

      Tagged with:

      • dist
      • distribution
      • randomize
      • constraint
      • value_range
    • 0 replies
    • 112 views
    • 
    • ljepson74
    • August 29

11. How to use a variable defined in one class into another class?

    By swapnilm, April 8, 2013
    • 6 replies
    • 8.9k views
    • 
    • David Black
    • August 26

12. SVA: implication vs. sequence. implication and delay.

    By ljepson74, August 26   

    • sva
    • assertion
    • (and 2 more)

      Tagged with:

      • sva
      • assertion
      • implication
      • delay
    • 0 replies
    • 81 views
    • 
    • ljepson74
    • August 26

13. randomize() with inside syntax

    By ljepson74, April 4, 2016   

    • randomize() with
    • randomize()
    • (and 1 more)

      Tagged with:

      • randomize() with
      • randomize()
      • inside
    • 4 replies
    • 31.3k views
    • 
    • ljepson74
    • August 21

14. Constraint across properties of array of objects

    By ljepson74, August 15   

    • constraint
    • sum
    • 5 replies
    • 138 views
    • 
    • ljepson74
    • August 20

15. UVM : transaction class and sequence_item class

    By Vinod_V, July 18   

    • uvm
    • verification
    • 0 replies
    • 127 views
    • 
    • Vinod_V
    • July 18

16. Explicit Prediction of Unmapped Registers

    By Henry, April 23
    • 4 replies
    • 211 views
    • 
    • Henry
    • July 13

17. Need help on agent architecture

    By santhosh2020, July 6
    • 1 reply
    • 87 views
    • 
    • chr_sue
    • July 7

18. Check if string is 'inside' an enum

    By ljepson74, June 21   

    • enum
    • string
    • (and 2 more)

      Tagged with:

      • enum
      • string
      • set
      • check
    • 4 replies
    • 307 views
    • 
    • dave_59
    • June 30

19. Determining change in signals

    By Nimesh, June 14   

    • systemverilog
    • verilog
    • 1 reply
    • 148 views
    • 
    • David Black
    • June 15

20. Use of wait statement

    By Nimesh, June 12   

    • systemverilog
    • verilog
    • (and 1 more)

      Tagged with:

      • systemverilog
      • verilog
      • read
    • 2 replies
    • 177 views
    • 
    • Nimesh
    • June 12

21. Transaction Logging

    By Nimesh, May 23   

    • uvm
    • systemverilog
    • (and 1 more)

      Tagged with:

      • uvm
      • systemverilog
      • systemverilog training
    • 1 reply
    • 107 views
    • 
    • chr_sue
    • May 24

22. Covergroup instance issue - system verilog coverage

    By smitgovani, May 12
    • 1 reply
    • 208 views
    • 
    • chr_sue
    • May 14

23. UVM_WARNING to stop simulation

    By bjoernohlau, April 24
    • 3 replies
    • 157 views
    • 
    • bjoernohlau
    • April 27

24. OSPI Register Model (unmapped register and non-register access)

    By Henry, April 21
    • 4 replies
    • 150 views
    • 
    • Henry
    • April 24

25. uvm_field_macros

    By kapil705, March 31   

    • uvm_field
    • uvm
    • 1 reply
    • 168 views
    • 
    • dave_59
    • April 1