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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

514 topics in this forum

  1. uvm_reg_field.get_access() method returns wrong value

    By Petr Kobiersky,
    • 0 replies
    • 15 views

  2. how to unpack payload?

    By swapnilm,
    • 12 replies
    • 12,716 views

  3. AHB , bus2reg , reg2bus in hrdata & hwdata

    By soleshka,
    • 1 reply
    • 34 views

  4. constraint dist 'others'

    By ljepson74,   
    • 3 replies
    • 553 views

  5. UVM_FATAL Errors

    By Hash,
    • 7 replies
    • 7,952 views

  6. UVM RAL implementation methodology for large designs

    By rgarciaf071,   
    • 1 reply
    • 144 views

  7. Unresolved reference to 'create_item' in $root.create_item !!!!

    By qinhailiang,
    • 2 replies
    • 3,351 views

  8. How can I print out Logs left-aligned?

    By karlzhao,
    • 2 replies
    • 1,564 views

  9. Possible bug: UVM 1.2,IEEE: uvm_transaction.svh, etc.

    By kaushalmodi,   
    • 2 replies
    • 181 views

  10. Volatile bit set for RO registers

    By Narendra,
    • 0 replies
    • 92 views

  11. monitor output is delayed due to run_phase ordering

    By Khushi,
    • 1 reply
    • 426 views

  12. Do we need to use two monitors one each for input and output

    By Khushi,
    • 1 reply
    • 298 views

  13. UVM phase jumping to extract phase

    By sharvil111,   
    • 1 reply
    • 1,160 views

  14. Cause of UVM Timeout

    By sas73,
    • 3 replies
    • 128 views

  15. drive same sequence to multiple driver

    By Khushi,
    • 2 replies
    • 440 views

  16. unsuccessful factory override

    By ori,
    • 2 replies
    • 151 views

  17. Alternate Scoreboarding approach

    By svuvmuser,   
    • 1 reply
    • 654 views

  18. End of test in UVM-1.2

    By asic_bg,
    • 0 replies
    • 481 views

  19. Behavior of uvm_sequence_base::kill method

    By Taichi Ishitani,
    • 0 replies
    • 104 views

  20. Returning event from virtual function

    By DanaL,
    • 1 reply
    • 160 views

  21. Property in assertion

    By venkatasubbarao_Sutrave,
    • 1 reply
    • 423 views

  22. Individual uvm_reg_field exclusion from uvm_reg_hw_reset_seq possible?

    By obajaj,
    • 1 reply
    • 350 views

  23. uvm_reg_bit_bash_seq

    By Suguna R,
    • 1 reply
    • 228 views

  24. How to read all the register in RAL model using reg_map?

    By nayan,
    • 1 reply
    • 214 views

  25. Multiple target sockets with multiple b_transport functions in one class?

    By basarts,
    • 4 replies
    • 202 views
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