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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

588 topics in this forum

  1. How create mutiple uvm_component instances of uvm_component array?

    By mrforever,
    • 4 replies
    • 5.6k views

  2. UVM verification... illegal assignment

    By Ravi_3,
    • 1 reply
    • 129 views

  3. Is data written on register used for APB protocol

    By M Prasanth,
    • 1 reply
    • 63 views

  4. Uvm factory registration disambiguation

    By bradpinn,   
    • 1 reply
    • 122 views

  5. Relationship between PSEL and PENABLE signals in the APB Protocol.

    By P.Ksagar,   
    • 1 reply
    • 201 views

  6. Argument problem of uvm_mem_region::burst_read() in uvm-1.2

    By Leon,   
    • 1 reply
    • 171 views

  7. uvm_report_object -- why only uvm_component based classed are derived from uvm_report and not uvm_sequence_item/uvm_transaction

    By dips1000,
    • 2 replies
    • 115 views

  8. Package for parametric design

    By iidolevy,
    • 4 replies
    • 850 views

  9. UVM with AMS: Best practice for handling OOMR DUT probes with different net types

    By Paul Miller,
    • 2 replies
    • 270 views

  10. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 4 replies
    • 1.6k views

  11. How to disable fork join or fork join_any after executed particular thread or process

    By Subbi Reddy Manne,
    • 2 replies
    • 466 views

  12. How to continue a test after getting UVM error

    By Prathyusha G,
    • 0 replies
    • 346 views

  13. Interface not being loaded into config db correctly

    By LastHorizon,
    • 2 replies
    • 527 views

  14. Preload all the DUT

    By Peter_vertlib,
    • 0 replies
    • 207 views

  15. How memory interaction between C Language in SV or UVM

    By Subbi Reddy Manne,   
    • 0 replies
    • 239 views

  16. In AXI, at what scenario can use out of order and outstanding transactions

    By Subbi Reddy Manne,   
    • 0 replies
    • 210 views

  17. How to read all the register in RAL model using reg_map?

    By nayan,
    • 2 replies
    • 4.2k views

  18. Analysis port in user callback class

    By ManMe,
    • 5 replies
    • 2.1k views

  19. Uvm ams

    By Cropty,
    • 1 reply
    • 160 views

  20. named event to trigger between class and module

    By ljepson74,   
    • 4 replies
    • 5.7k views

  21. Different registers with same register name present in different submap of register

    By asiclover,   
    • 0 replies
    • 310 views

  22. good technique to generate a random delay?

    By c4brian,
    • 11 replies
    • 25.6k views

  23. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 264 views

  24. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 260 views

  25. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 1.1k views
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