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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

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548 topics in this forum

  1. field.mirror() task not working as expected

    By shreyasraju,   
    • 7 replies
    • 3.4k views

  2. Reduction operator in case of one-bit vector

    By Thomas Kruse,
    • 2 replies
    • 32 views

  3. Array of SystemVerilog Interface

    By Thomas Kruse,
    • 2 replies
    • 48 views

  4. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74,   
    • 4 replies
    • 1.4k views

  5. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K,
    • 1 reply
    • 63 views

  6. reg.randomize doesn't work for some regs

    By Weicai,
    • 0 replies
    • 37 views

  7. UVM_FATAL Errors

    By Hash,
    • 8 replies
    • 9.6k views

  8. Could not find call of check_config_usage in UVM library

    By supal,
    • 2 replies
    • 81 views

  9. Learning System Verilog from scratch

    By Dexy10,
    • 1 reply
    • 99 views

  10. Verilog/SystemVerilog Configuration default liblist question

    By cliffc,   
    • 2 replies
    • 75 views

  11. Verilog bug issue

    By Tarzan,
    • 2 replies
    • 136 views

  12. How to access register file array data using bind module

    By Dina Emadeldin,
    • 1 reply
    • 119 views

  13. Array of covergroup wrapper objects. Problems.

    By ljepson74,   
    • 1 reply
    • 257 views

  14. Consequence of not to be an "assignment-like context"

    By Thomas Kruse,
    • 0 replies
    • 53 views

  15. "uvm sequence library" vs "virtual sequence"

    By Nadun,   
    • 1 reply
    • 114 views

  16. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 2 replies
    • 131 views

  17. CAN bus verification

    By Sachin0509,
    • 0 replies
    • 66 views

  18. $system() function return value OR Setting a random sim seed within SystemVerilog code using wallclock time.

    By ljepson74,   
    • 8 replies
    • 539 views

  19. SeqA |-> SeqA may not happen again before the first of SeqB or SeqC

    By ljepson74,   
    • 0 replies
    • 126 views

  20. “dist”. Can a value_range be a list in a randomization distribution?

    By ljepson74,   
    • 0 replies
    • 201 views

  21. How to use a variable defined in one class into another class?

    By swapnilm,
    • 6 replies
    • 9.2k views

  22. SVA: implication vs. sequence. implication and delay.

    By ljepson74,   
    • 0 replies
    • 139 views

  23. randomize() with inside syntax

    By ljepson74,   
    • 4 replies
    • 32.5k views

  24. Constraint across properties of array of objects

    By ljepson74,   
    • 5 replies
    • 198 views

  25. UVM : transaction class and sequence_item class

    By Vinod_V,   
    • 0 replies
    • 165 views
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