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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

585 topics in this forum

  1. Relationship between PSEL and PENABLE signals in the APB Protocol.

    By P.Ksagar,   
    • 1 reply
    • 60 views

  2. Argument problem of uvm_mem_region::burst_read() in uvm-1.2

    By Leon,   
    • 1 reply
    • 133 views

  3. uvm_report_object -- why only uvm_component based classed are derived from uvm_report and not uvm_sequence_item/uvm_transaction

    By dips1000,
    • 2 replies
    • 59 views

  4. Package for parametric design

    By iidolevy,
    • 4 replies
    • 702 views

  5. UVM with AMS: Best practice for handling OOMR DUT probes with different net types

    By Paul Miller,
    • 2 replies
    • 164 views

  6. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 4 replies
    • 1.1k views

  7. How to disable fork join or fork join_any after executed particular thread or process

    By Subbi Reddy Manne,
    • 2 replies
    • 188 views

  8. How to continue a test after getting UVM error

    By Prathyusha G,
    • 0 replies
    • 232 views

  9. Interface not being loaded into config db correctly

    By LastHorizon,
    • 2 replies
    • 302 views

  10. Preload all the DUT

    By Peter_vertlib,
    • 0 replies
    • 150 views

  11. How memory interaction between C Language in SV or UVM

    By Subbi Reddy Manne,   
    • 0 replies
    • 165 views

  12. In AXI, at what scenario can use out of order and outstanding transactions

    By Subbi Reddy Manne,   
    • 0 replies
    • 158 views

  13. How to read all the register in RAL model using reg_map?

    By nayan,
    • 2 replies
    • 3.4k views

  14. Analysis port in user callback class

    By ManMe,
    • 5 replies
    • 2k views

  15. Uvm ams

    By Cropty,
    • 1 reply
    • 129 views

  16. named event to trigger between class and module

    By ljepson74,   
    • 4 replies
    • 5.4k views

  17. Different registers with same register name present in different submap of register

    By asiclover,   
    • 0 replies
    • 250 views

  18. good technique to generate a random delay?

    By c4brian,
    • 11 replies
    • 24.7k views

  19. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 210 views

  20. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 177 views

  21. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 683 views

  22. How to create constraint for following

    By venkatasubbarao_Sutrave,   
    • 0 replies
    • 213 views

  23. sequence is not running - make sure sequencer name 'correct'

    By ljepson74,   
    • 3 replies
    • 5k views

  24. USB 3.0 (xHCI)

    By M s sai kamesh,
    • 1 reply
    • 194 views

  25. Confused between Definitions

    By Hany Salah,
    • 10 replies
    • 6.1k views
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