UVM SystemVerilog Discussions

564 topics in this forum

1. Help needed in setting up a Hello_World UVM example project in RIVIERA-PRO 2014-10.

   By nasirkhanpak25, October 20
   • 2 replies
   • 36 views
   • 
   • nasirkhanpak25
   • Wednesday at 06:39 PM

2. how can we print in which phase we are in UVM

   By Serya, September 22
   • 1 reply
   • 65 views
   • 
   • chr_sue
   • Wednesday at 03:19 PM

3. DPI guideline for various programming language

   By Eric Hsu, August 30   

   • dpi
   • systemverilog
   • 3 replies
   • 186 views
   • 
   • Eric Hsu
   • September 14

4. Simulation hang due to "run_phase" not exiting

   By ankurraj, July 28
   • 3 replies
   • 231 views
   • 
   • tfitz
   • July 28

5. Sft constraint vs weighted constraint

   By SV_UVM_Infant, July 9
   • 2 replies
   • 124 views
   • 
   • SV_UVM_Infant
   • July 26

6. How to use a variable defined in one class into another class?

   By swapnilm, April 8, 2013
   • 7 replies
   • 10.4k views
   • 
   • Yuri
   • July 26

7. null value when trying to get register from top reg map by get_reg_by_offset

   By Ai_Ar, June 22   

   • register model
   • uvm
   • (and 1 more)

     Tagged with:

     • register model
     • uvm
     • adapter
   • 0 replies
   • 128 views
   • 
   • Ai_Ar
   • June 22

8. How to access the instance ID of a class from a base_class, whose child class is instantiated inside.

   By Sujitha, June 22
   • 0 replies
   • 74 views
   • 
   • Sujitha
   • June 22

9. How do I get multiple transactions if register width is wider or narrower than bus width?

   By qurax, June 12   

   • uvm
   • register model
   • (and 2 more)

     Tagged with:

     • uvm
     • register model
     • register layer
     • systemverilog
   • 0 replies
   • 117 views
   • 
   • qurax
   • June 12

10. UVM randomise specific extended class only not other classes

    By Ahmad Fahad, June 10
    • 1 reply
    • 87 views
    • 
    • dave_59
    • June 10

11. Multiple target sockets with multiple b_transport functions in one class?

    By Bas Arts, May 20, 2019
    • 6 replies
    • 748 views
    • 
    • David Black
    • June 7

12. any restrictions on expression in wait(expression)?

    By mastrick, September 26, 2012
    • 6 replies
    • 8.9k views
    • 
    • dave_59
    • June 7

13. The question on reactive slave

    By VVdemajia, September 21, 2015   

    • reactive slave AHB
    • 5 replies
    • 1.4k views
    • 
    • peegu
    • April 28

14. What happen if read access is performed on write-only register?

    By meah, April 16
    • 1 reply
    • 149 views
    • 
    • chr_sue
    • April 16

15. Hierarchical names in constant expression

    By Thomas Kruse, March 24
    • 1 reply
    • 184 views
    • 
    • dave_59
    • March 29

16. Transaction timer expired (WDT)

    By Yan, March 28
    • 5 replies
    • 175 views
    • 
    • David Black
    • March 29

17. Printer

    By bl4ckp3rl, March 25
    • 1 reply
    • 117 views
    • 
    • Mark Strickland
    • March 25

18. SystemVerilog Assertions not getting included

    By Ankit Shah, March 24
    • 2 replies
    • 117 views
    • 
    • Ankit Shah
    • March 25

19. queue/array randomize

    By shanghai1943, March 11   

    • randomize
    • 3 replies
    • 255 views
    • 
    • shanghai1943
    • March 11

20. uvm_resource_db confusion

    By shanghai1943, March 10   

    • uvm_config_db/uvm_resource_db
    • 2 replies
    • 212 views
    • 
    • David Black
    • March 10

21. field.mirror() task not working as expected

    By shreyasraju, March 7, 2014   

    • Mirror
    • RAL
    • (and 1 more)

      Tagged with:

      • Mirror
      • RAL
      • uvm_reg_field
    • 7 replies
    • 3.8k views
    • 
    • Mark Strickland
    • March 2

22. Reduction operator in case of one-bit vector

    By Thomas Kruse, February 25
    • 2 replies
    • 129 views
    • 
    • Thomas Kruse
    • February 25

23. Array of SystemVerilog Interface

    By Thomas Kruse, February 16
    • 2 replies
    • 417 views
    • 
    • Thomas Kruse
    • February 16

24. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74, May 1, 2018   

    • time slot
    • time step
    • (and 1 more)

      Tagged with:

      • time slot
      • time step
      • lrm
    • 4 replies
    • 1.7k views
    • 
    • dave_59
    • February 16

25. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K, February 13
    • 1 reply
    • 209 views
    • 
    • chr_sue
    • February 15