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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

581 topics in this forum

  1. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 4 replies
    • 775 views

  2. How to disable fork join or fork join_any after executed particular thread or process

    By Subbi Reddy Manne,
    • 2 replies
    • 49 views

  3. How to continue a test after getting UVM error

    By Prathyusha G,
    • 0 replies
    • 83 views

  4. Interface not being loaded into config db correctly

    By LastHorizon,
    • 2 replies
    • 95 views

  5. Preload all the DUT

    By Peter_vertlib,
    • 0 replies
    • 92 views

  6. How memory interaction between C Language in SV or UVM

    By Subbi Reddy Manne,   
    • 0 replies
    • 72 views

  7. In AXI, at what scenario can use out of order and outstanding transactions

    By Subbi Reddy Manne,   
    • 0 replies
    • 77 views

  8. How to read all the register in RAL model using reg_map?

    By nayan,
    • 2 replies
    • 2.8k views

  9. Analysis port in user callback class

    By ManMe,
    • 5 replies
    • 1.8k views

  10. Uvm ams

    By Cropty,
    • 1 reply
    • 72 views

  11. named event to trigger between class and module

    By ljepson74,   
    • 4 replies
    • 5.2k views

  12. Different registers with same register name present in different submap of register

    By asiclover,   
    • 0 replies
    • 155 views

  13. good technique to generate a random delay?

    By c4brian,
    • 11 replies
    • 23.9k views

  14. Issue: Functionality of Cross coverage

    By Abdul Razak H S,
    • 2 replies
    • 138 views

  15. Base address is not getting picked from RAL for a memory

    By Chinmayks17,
    • 0 replies
    • 96 views

  16. Error: uninitialized virtual interface object at time 0 in file driver.sv line 29

    By Abdul Razak H S,
    • 2 replies
    • 346 views

  17. How to create constraint for following

    By venkatasubbarao_Sutrave,   
    • 0 replies
    • 127 views

  18. sequence is not running - make sure sequencer name 'correct'

    By ljepson74,   
    • 3 replies
    • 4.7k views

  19. USB 3.0 (xHCI)

    By M s sai kamesh,
    • 1 reply
    • 126 views

  20. Confused between Definitions

    By Hany Salah,
    • 10 replies
    • 5.8k views

  21. Using get_reg_by_name() API for registers instantiated in a UVM register file

    By ankurraj,
    • 1 reply
    • 507 views

  22. uvm_reg_map does not clean up after itself when there's a parent sequence set

    By Georgegg,
    • 0 replies
    • 170 views

  23. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 3 replies
    • 685 views

  24. referencing an array of uvm_analysis_imp in a scoreboard

    By makers78,
    • 7 replies
    • 11.2k views

  25. [System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array .

    By rajivdesh,   
    • 2 replies
    • 650 views
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