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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

528 topics in this forum

  1. Explicit Prediction of Unmapped Registers

    By Henry,
    • 4 replies
    • 99 views

  2. Need help on agent architecture

    By santhosh2020,
    • 1 reply
    • 32 views

  3. Check if string is 'inside' an enum

    By ljepson74,   
    • 4 replies
    • 73 views

  4. Determining change in signals

    By Nimesh,   
    • 1 reply
    • 93 views

  5. Use of wait statement

    By Nimesh,   
    • 2 replies
    • 83 views

  6. Transaction Logging

    By Nimesh,   
    • 1 reply
    • 59 views

  7. Covergroup instance issue - system verilog coverage

    By smitgovani,
    • 1 reply
    • 82 views

  8. UVM_WARNING to stop simulation

    By bjoernohlau,
    • 3 replies
    • 88 views

  9. OSPI Register Model (unmapped register and non-register access)

    By Henry,
    • 4 replies
    • 99 views

  10. uvm_field_macros

    By kapil705,   
    • 1 reply
    • 77 views

  11. UVM RAL uvm_mem 8 bits wide memories mapped into map with 32 bits word

    By KristinaD,   
    • 0 replies
    • 113 views

  12. SV-DPI and co-routine

    By Robert.g.Liu,
    • 0 replies
    • 100 views

  13. Erroneous buffer size comparison in uvm_sequencer_param_base.svh

    By basarts,
    • 0 replies
    • 86 views

  14. [REG_PREDICT_COLLISION] Collision detected for register ...

    By Ryan100,
    • 1 reply
    • 257 views

  15. uvm_reg_field.get_access() method returns wrong value

    By Petr Kobiersky,
    • 1 reply
    • 164 views

  16. how to unpack payload?

    By swapnilm,
    • 12 replies
    • 13,392 views

  17. AHB , bus2reg , reg2bus in hrdata & hwdata

    By soleshka,
    • 1 reply
    • 254 views

  18. constraint dist 'others'

    By ljepson74,   
    • 3 replies
    • 1,450 views

  19. UVM_FATAL Errors

    By Hash,
    • 7 replies
    • 8,714 views

  20. UVM RAL implementation methodology for large designs

    By rgarciaf071,   
    • 1 reply
    • 396 views

  21. Unresolved reference to 'create_item' in $root.create_item !!!!

    By qinhailiang,
    • 2 replies
    • 3,506 views

  22. How can I print out Logs left-aligned?

    By karlzhao,
    • 2 replies
    • 2,077 views

  23. Possible bug: UVM 1.2,IEEE: uvm_transaction.svh, etc.

    By kaushalmodi,   
    • 2 replies
    • 657 views

  24. Volatile bit set for RO registers

    By Narendra,
    • 0 replies
    • 214 views

  25. monitor output is delayed due to run_phase ordering

    By Khushi,
    • 1 reply
    • 611 views
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