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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

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534 topics in this forum

  1. $system() function return value OR Setting a random sim seed within SystemVerilog code using wallclock time.

    By ljepson74,   
    • 8 replies
    • 146 views

  2. SeqA |-> SeqA may not happen again before the first of SeqB or SeqC

    By ljepson74,   
    • 0 replies
    • 45 views

  3. “dist”. Can a value_range be a list in a randomization distribution?

    By ljepson74,   
    • 0 replies
    • 57 views

  4. How to use a variable defined in one class into another class?

    By swapnilm,
    • 6 replies
    • 8.6k views

  5. SVA: implication vs. sequence. implication and delay.

    By ljepson74,   
    • 0 replies
    • 54 views

  6. randomize() with inside syntax

    By ljepson74,   
    • 4 replies
    • 30.4k views

  7. Constraint across properties of array of objects

    By ljepson74,   
    • 5 replies
    • 107 views

  8. UVM : transaction class and sequence_item class

    By Vinod_V,   
    • 0 replies
    • 114 views

  9. Explicit Prediction of Unmapped Registers

    By Henry,
    • 4 replies
    • 159 views

  10. Need help on agent architecture

    By santhosh2020,
    • 1 reply
    • 68 views

  11. Check if string is 'inside' an enum

    By ljepson74,   
    • 4 replies
    • 173 views

  12. Determining change in signals

    By Nimesh,   
    • 1 reply
    • 123 views

  13. Use of wait statement

    By Nimesh,   
    • 2 replies
    • 125 views

  14. Transaction Logging

    By Nimesh,   
    • 1 reply
    • 88 views

  15. Covergroup instance issue - system verilog coverage

    By smitgovani,
    • 1 reply
    • 146 views

  16. UVM_WARNING to stop simulation

    By bjoernohlau,
    • 3 replies
    • 128 views

  17. OSPI Register Model (unmapped register and non-register access)

    By Henry,
    • 4 replies
    • 124 views

  18. uvm_field_macros

    By kapil705,   
    • 1 reply
    • 113 views

  19. UVM RAL uvm_mem 8 bits wide memories mapped into map with 32 bits word

    By KristinaD,   
    • 0 replies
    • 142 views

  20. SV-DPI and co-routine

    By Robert.g.Liu,
    • 0 replies
    • 141 views

  21. Erroneous buffer size comparison in uvm_sequencer_param_base.svh

    By basarts,
    • 0 replies
    • 107 views

  22. [REG_PREDICT_COLLISION] Collision detected for register ...

    By Ryan100,
    • 1 reply
    • 315 views

  23. uvm_reg_field.get_access() method returns wrong value

    By Petr Kobiersky,
    • 1 reply
    • 195 views

  24. how to unpack payload?

    By swapnilm,
    • 12 replies
    • 13.6k views

  25. AHB , bus2reg , reg2bus in hrdata & hwdata

    By soleshka,
    • 1 reply
    • 323 views
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