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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

512 topics in this forum

  1. constraint dist 'others'

    By ljepson74,   
    • 3 replies
    • 354 views

  2. UVM_FATAL Errors

    By Hash,
    • 7 replies
    • 7,767 views

  3. UVM RAL implementation methodology for large designs

    By rgarciaf071,   
    • 1 reply
    • 103 views

  4. Unresolved reference to 'create_item' in $root.create_item !!!!

    By qinhailiang,
    • 2 replies
    • 3,330 views

  5. How can I print out Logs left-aligned?

    By karlzhao,
    • 2 replies
    • 1,455 views

  6. Possible bug: UVM 1.2,IEEE: uvm_transaction.svh, etc.

    By kaushalmodi,   
    • 2 replies
    • 147 views

  7. Volatile bit set for RO registers

    By Narendra,
    • 0 replies
    • 76 views

  8. monitor output is delayed due to run_phase ordering

    By Khushi,
    • 1 reply
    • 407 views

  9. Do we need to use two monitors one each for input and output

    By Khushi,
    • 1 reply
    • 276 views

  10. UVM phase jumping to extract phase

    By sharvil111,   
    • 1 reply
    • 1,080 views

  11. Cause of UVM Timeout

    By sas73,
    • 3 replies
    • 110 views

  12. drive same sequence to multiple driver

    By Khushi,
    • 2 replies
    • 419 views

  13. unsuccessful factory override

    By ori,
    • 2 replies
    • 133 views

  14. Alternate Scoreboarding approach

    By svuvmuser,   
    • 1 reply
    • 639 views

  15. End of test in UVM-1.2

    By asic_bg,
    • 0 replies
    • 343 views

  16. Behavior of uvm_sequence_base::kill method

    By Taichi Ishitani,
    • 0 replies
    • 78 views

  17. Returning event from virtual function

    By DanaL,
    • 1 reply
    • 131 views

  18. Property in assertion

    By venkatasubbarao_Sutrave,
    • 1 reply
    • 398 views

  19. Individual uvm_reg_field exclusion from uvm_reg_hw_reset_seq possible?

    By obajaj,
    • 1 reply
    • 327 views

  20. uvm_reg_bit_bash_seq

    By Suguna R,
    • 1 reply
    • 213 views

  21. How to read all the register in RAL model using reg_map?

    By nayan,
    • 1 reply
    • 186 views

  22. Multiple target sockets with multiple b_transport functions in one class?

    By basarts,
    • 4 replies
    • 182 views

  23. Transaction Design Patterns

    By sas73,
    • 17 replies
    • 508 views

  24. Constrained Random Performance

    By sas73,
    • 4 replies
    • 386 views

  25. Functional coverage- VCS

    By vaibhav0901,
    • 3 replies
    • 665 views
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