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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

Followers 15

555 topics in this forum

  1. The question on reactive slave

    By VVdemajia,   
    • 5 replies
    • 1.3k views

  2. What happen if read access is performed on write-only register?

    By meah,
    • 1 reply
    • 60 views

  3. Hierarchical names in constant expression

    By Thomas Kruse,
    • 1 reply
    • 74 views

  4. Transaction timer expired (WDT)

    By Yan,
    • 5 replies
    • 60 views

  5. Printer

    By bl4ckp3rl,
    • 1 reply
    • 61 views

  6. SystemVerilog Assertions not getting included

    By Ankit Shah,
    • 2 replies
    • 44 views

  7. queue/array randomize

    By shanghai1943,   
    • 3 replies
    • 94 views

  8. uvm_resource_db confusion

    By shanghai1943,   
    • 2 replies
    • 92 views

  9. field.mirror() task not working as expected

    By shreyasraju,   
    • 7 replies
    • 3.5k views

  10. Reduction operator in case of one-bit vector

    By Thomas Kruse,
    • 2 replies
    • 51 views

  11. Array of SystemVerilog Interface

    By Thomas Kruse,
    • 2 replies
    • 115 views

  12. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74,   
    • 4 replies
    • 1.5k views

  13. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K,
    • 1 reply
    • 90 views

  14. reg.randomize doesn't work for some regs

    By Weicai,
    • 0 replies
    • 63 views

  15. UVM_FATAL Errors

    By Hash,
    • 8 replies
    • 9.9k views

  16. Could not find call of check_config_usage in UVM library

    By supal,
    • 2 replies
    • 107 views

  17. Learning System Verilog from scratch

    By Dexy10,
    • 1 reply
    • 144 views

  18. Verilog/SystemVerilog Configuration default liblist question

    By cliffc,   
    • 2 replies
    • 101 views

  19. Verilog bug issue

    By Tarzan,
    • 2 replies
    • 157 views

  20. How to access register file array data using bind module

    By Dina Emadeldin,
    • 1 reply
    • 142 views

  21. Array of covergroup wrapper objects. Problems.

    By ljepson74,   
    • 1 reply
    • 365 views

  22. Consequence of not to be an "assignment-like context"

    By Thomas Kruse,
    • 0 replies
    • 62 views

  23. "uvm sequence library" vs "virtual sequence"

    By Nadun,   
    • 1 reply
    • 149 views

  24. Question : Regarding UVM IEEE stop_sequences() vs `UVM_CREAT(seqItem, seqr)

    By DV-E,
    • 2 replies
    • 185 views

  25. CAN bus verification

    By Sachin0509,
    • 0 replies
    • 78 views
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