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  2. TGC is 'The Good Core' family of RISC-V cores of MINRES Technolgis GmbH. The VP-Vibes organization at Github is for any project related to Virtual Prototypes. So the SystemC-Components library comes with SystemC utilities, components like register and generic bus targets as well as on-chip interconnect protocol definitions. The VPV-Peripherals provides peripherals which can be used in building VPs while the TGC-VP assembles all these components into a VP. Parts of the VP, in detail the ISS and its infrastructure, is being used as reference model to verify the RTL implementation(s). For this we use an insturction stream generator and a response checker (see also here).
  3. tri-state logic is not synthesizable. But if you use a 2-bit vector where one bit shows activity and one bit the value this can be synthesized... But it doubles the number af wires and depending on the gate logic the size of the logic. This may be wroked around by designing a custom cell for the standard cell library. After it is characterized the cell might be used by the synthesizer.
  4. I am attempting to model a three-state system in SystemC, adapting the biological behavior to gates. (The idea is similar to neuron synapses' biological behavior: I want to use pulses instead of levels.) Say, by default a two-input gate has its both inputs (synapses) and its output (axon) in state Z. If a 'spike' arrives (an event) to one of its inputs, for the duration of the spike, the input is set to 0 or 1 (as received) for a while, then the input changes back to Z. The gate remembers its inputs, and when it receives its second input, it sets its output to the calculated value for a while, then it changes back to Z (and resets input latching). Is this synthesizable? Can its 'real estate' demand be estimated? (How much such a solution increases number of gates in the circuit?) I.e. the level sequence is Z-0/1-Z, instead of 0-1-0.
  5. Try using the function void get_objectors( ref uvm_object list[$] ) method to see which component (if any) is still objecting. Although I'm pretty sure that the message you're showing would only print after all objections have been lowered.
  6. If all "run_phases" have completed, doesn't it implicitly imply that all objections are dropped ? What can be causing the simulation to still hang ? The testbench has large number of vendor VIPs/custom drivers and monitors, every component having its own objection mechanism. It is not possible to paste the code here.
  7. The message you are showing indicates only that all run_phases have been completed. It doies not say anything about dropping objections. Where did you insert the objection mechanism? Please show some mor code, especiually from the driver and the monitor.
  8. Hi, I am working on a UVM testbench. I am getting a hang issue in one of the simulations. I get the following print in the log: "reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase" Even after this print message, I see that time is still advancing in the test and it is not proceeding to the next phase. My query is - Does this print message not guarantee that all objections are dropped in the test ? What can be the possible reasons that the simulation is not proceeding to the next phase ?
  9. create new package, declare there some variables, import this package to any class, which wants access to that variables. Enjoy 🙂
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  11. Accellera Board Approves Security Annotation for Electronic Design Integration Standard 1.0 for Release New standard to identify security concerns for IP providers Elk Grove, Calif., July 14, 2021 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Board of Directors has approved the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0 for release. Developed by the IP Security Assurance (IPSA) Working Group, the new standard is available for immediate download at no cost. Read the full press release here ->
  12. Updating predictor sounds a good idea . Did you keep the adapter code as you mentioned or changed it back to standard
  13. @Eyck, Looking at the GitHub you provided, what's the instructions to generate RTL and verification test cases? I am not familiar with what TGC cores are. Does the RTL and verification generation come with the libraries in these TGC core libraries? I think the Vibes are just for the interconnects like AXI, maybe for the cores.
  14. Thanks Guys for the links!
  15. After the SystemC Evolution Fika panel discussion on Model Libraries, the Accellera SystemC Common Practices Subgroup has announced a call for contributions. We would appreciate contributions to collect industry best practices on modelling registers in SystemC. Our preference would be to receive a prototype (though it does not have to be 'complete') and it should also be useful to the SystemC CCI Working Group as an example implementation of a register that can be used to define a Register-discovery/Inspection API. If you or your organization has a way to model registers that you would like to share with the rest of the community, then we would like to hear from you. The call for contributions began on July 2 and will remain open until the end of August 2021. We will gladly take contributions of any form, as long as it complies with the Accellera IP Rights Policy. It would also help if you can give us an indication as soon as possible that you or your organization would like to contribute. For more information or to send a contribution, please contact the SystemC Common Practices sub working group chair: mark.burton@greensocs.com
  16. I see that the write is happening correctly in the RTL, but the get called after write doesn't returns "0" instead of the write value. the mirror(since explicit prediction) called after read returns the correct value that was written in. reg_model.amp_reg.ampstate_8_reg_blk.svm_control_reg.write(.status(status),.value(in_data0), .extension(ext),.parent(this)); ctrl_value = reg_model.amp_reg.reg_blk.control_reg.get(); reg_model.amp_reg.amp_reg.reg_blk.control_reg.read(.status(status), .value(read_data),.extension(ext),.parent(this)); value = reg_model.amp_reg.reg_blk.control_reg.get_mirrored_value(); `uvm_info("reg_seq", $sformatf("The mirror value is:%0h",value), UVM_HIGH) if(ctrl_value == value) begin `uvm_info("reg_seq", "svm_control_reg read back value matches write ", UVM_LOW) end
  17. Hello, I have checked and found this to be true "producer_write_share_sc_fifo() writes multiple messages to sc_fifo1, sc_fifo2 and sc_fifo3. I think I can expect each of method1, method2 and method3 to be called once at least.". I just need a reconfirmation. Regards Moreshwar
  18. Thanks for the clarifications. I will try to check your clarifications in code. I may have some questions after reading the specification with respect to your clarification and my trials. I just wanted a reconfirmation for the following If producer_write_share_sc_fifo() writes to one sc_fifo, then there is one notification irrespective of number of entries written to that sc_fifo If producer_write_share_sc_fifo() writes to more than one sc_fifo, then there will be one notification per sc_fifo assuming there is one method per sc_fifo that is sensitive to the data_written_event() of the sc_fifo. To be clearer with an example: If have 3 sc_fifos: sc_fifo1, sc_fifo2 and sc_fifo3 method1 is sensitive to data_written_event of sc_fifo1 method2 is sensitive to data_written_event of sc_fifo2 method3 is sensitive to data_written_event of sc_fifo3 producer_write_share_sc_fifo() writes multiple messages to sc_fifo1, sc_fifo2 and sc_fifo3. I think I can expect each of method1, method2 and method3 to be called once at least.
  19. Yes, you are writing 2 elements into the fifo in the same evaluation phase. This results in a single notification of the data wrtitten event. The returned value tells you if the write was succesfull or not. How to react on that depends on your model. At least you have to try it again at a later time (e.g. when the fifo has room for the new element). The delta cycle does not change. But I guess you mean when does the function return. For this you can consult the LRM. But in short: nb_write returns immediately, it is non-blockin (or nb). Therefore you can use it in an SC_METHOD. write is blocking which means internally wait is called and it returns once the element has been placed in the fifo. Therefor write can only be used in SC_THREAD since the call to wait() is not allowed in SC_METHOD.
  20. Hello, I am learning sc_fifo and I cant find anything on below points. it will be helpful if someone can answer or at least point me where i can get more info. What i have done: 1. I have a sc_fifo shared between producer and consumer the consumer is declared sensitive to sc_fifo data_written_event by using SC_METHOD(consumer_read_shared_sc_fifo) sensitive << shared_sc_fifo.data_written_event() 2. I write 3 entries to shared_sc_fifo within same function producer_write_shared_sc_fifo as follows shared_sc_fifo.write(msg1) shared_sc_fifo.write(msg2) where msg1 and msg 2 are the two messages of struct Message I have defined What noticing is that the function producer_write_shared_sc_fifo returns successfully implying that data is now in shared_sc_fifo My Questions/ Doubts are 1. I am expecting that consumer_read_shared_sc_fifo will be called twice but it is called once even though the available count (value returned by num_available() method) is 2. I think this is because i am writing in the same function. Am I right? 2. I am thinking of calling nb_write() instead of write() as I dont want to block if there is insufficient space . However, I am not sure the behaviour of caller i.e., producer_write_share_sc_fifo() in case space is not available. i know it will return false. What I am not sure is, what should be the behaviour in case nb_write returns false. Do i have to try this nb_write again? 3. When does the delta cycle end for write nb_write Regards Moreshwar
  21. Hi, how can I set up a constraint so randomization only generates odd numbers? Since, the operator % is not implemented I wonder what it is the mode idiomatic way to do it. Thanks
  22. Thanks for your suggestions, I reported them to the SystemC Language Working Group.
  23. The version is SystemC 2.3.3 (Includes TLM)
  24. We found several possible problems in the pkt_switch routine under the example folder. Here are my suggestions. First, in the fifo.cpp file, the pkt_out method lacks the logic to reset the "full", which results in no more data being read after the fifo is full. Second, in Line 204, 210, 216 in the switch.cpp file, the judgment condition of R1.free, R2.free, R3.free is wrong, which causes some data packets to be lost too early. The code is modified as follows: pkt fifo::pkt_out() { pkt temp; temp = regs[0]; if (--pntr == 0) empty = true; else { regs[0] = regs[1]; regs[1] = regs[2]; regs[2] = regs[3]; full = false; } return(temp); } /////write the register values to output fifos//////////// if ((!R0.free) && (R0.val.dest0) && (!q0_out.full)) { q0_out.pkt_in(R0.val); R0.val.dest0 = false; if (!(R0.val.dest0|R0.val.dest1|R0.val.dest2|R0.val.dest3)) R0.free = true; } if ((!R1.free) && (R1.val.dest1) && (!q1_out.full)) { q1_out.pkt_in(R1.val); R1.val.dest1 = false; if (!(R1.val.dest0|R1.val.dest1|R1.val.dest2|R1.val.dest3)) R1.free = true; } if ((!R2.free) && (R2.val.dest2) && (!q2_out.full)) { q2_out.pkt_in(R2.val); R2.val.dest2 = false; if (!(R2.val.dest0|R2.val.dest1|R2.val.dest2|R2.val.dest3)) R2.free = true; } if ((!R3.free) && (R3.val.dest3) && (!q3_out.full)) { q3_out.pkt_in(R3.val); R3.val.dest3 = false; if (!(R3.val.dest0|R3.val.dest1|R3.val.dest2|R3.val.dest3)) R3.free = true; } At the same time, I also submitted the modified code on github
  25. There are quite few more RISC-V ISS/VPs, all based on SystemC. E.g.: ETISS of TU München (https://github.com/VP-Vibes/etiss) TGC-VP of MINRES (https://github.com/VP-Vibes/TGC-VP)
  26. The group of Daniel Große from University of Bremen and now Johannes Kepler University in Linz has released a RISC-V-based virtual prototype under MIT license, which could be of interest for you.
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