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  2. Can a single constraint be used across an array of objects? i.e. affecting the relation between a property which exists in each of those objects? I'm trying to do something like an array reduction or sum, but instead of performing it on an array, performing it on the properties of objects in an array. My goal is to better understand the capabilities of constraints. Example below: (I do not show my failed attempts.) //Class animal_c has a property "weight". //A dynamic array is generated where each element points to an animal. //The cumulative weight of the animals should be 100. //How can this be done with constraints? //Can a constraint expression reference properties referenced by handles? // //My goal is to better understand contraints, so I attempt to stuff as much as possible into the constraints. module top; class animal_c; rand int weight; constraint weight_legal_c {weight>1; weight<40;} //allowed weight per animal. function void show(); $display("animal weight:%2d", weight); endfunction endclass class group_of_animals_c; rand animal_c animal_da[]; constraint number_of_animals_c { animal_da.size() inside {[3:5]}; } //As I understand, array objects cannot be constructed in the randomize call that determines the array size. (T or F?) //so, post_randomize seems the natural place to construct the objects in the array. function void post_randomize(); foreach(animal_da[iii]) begin animal_da[iii]=new(); //create each object of array assert(animal_da[iii].randomize()); end endfunction function void show_group(); foreach(animal_da[iii]) animal_da[iii].show(); endfunction endclass initial begin group_of_animals_c group_m; group_m = new(); assert(group_m.randomize()); group_m.show_group(); end endmodule https://www.edaplayground.com/x/4Dx5
  3. Hi Erwin, Thanks for your answer. Your answer is very helpful to me. I modified register description based on your answer. (addressUnitBits 8 -> 16) Q1)Is the description below right? [ip-xact information] - slave interface. bitInLau : 8 - addressblock width : 16 - addressUnitBits : 8 -> 16 - register name A_0: - register offset : 0 - register size : 16 - register name A_1: - register offset : 1 - register size : 16 - register name B_0: - register offset : 2 - register size : 16 - register name B_1: - register offset : 3 - register size : 16 addr_offset@ip-xact address @ slave interface access register 0x0 0x0 A_0[15:0] 0x1 0x2 A_1[15:0] 0x2 0x4 B_0[15:0] 0x3 0x6 B_1[15:0] Q2) If isData is not define, addressblock's width same as data bus width. Is it right?
  4. Yesterday
  5. Hi Suhyun, Your register descriptions are not valid. You have addressUnitBits set to 8 meaning that the unit of addressing is 8 bits. That means that your register offset should 0, 2, 4, … In your example, they are 0, 1, 2, … while the registers are 16 bits. That means register 0 occupies bits 0 to 15, register 1 occupies bits 8 to 23, and so on. Hence, they overlap. The address block width indicates the maximum number of bits that can be accessed in a single transaction. The data bus width can be different. Your bus interface contains port maps. The logical ports in the port maps can have qualifiers. One of the qualifiers is isData. So you can look at the number of bits of the physical port that is mapped to the logical port with the isData qualifier. Best regards, Erwin
  6. The above descriptoin have probelm about SCR7.5... (The size of any register shall be no greater than the width of the containing address block.) [ip-xact information] - slave interface. bitInLau : 8 - addressblock width : 16 - addressUnitBits : 8 - register name A_0: - register offset : 0 - register size : 16 - register name A_1: - register offset : 1 - register size : 16 - register name B_0: - register offset : 2 - register size : 16 - register name B_1: - register offset : 3 - register size : 16 addr_offset@ip-xact address @ slave interface access register 0x0 0x0 A_0 0x1 0x2 A_1 0x2 0x4 B_0 0x3 0x6 B_1 Anyway, ignore the above question. Q1) Is value of addressblock's width same as data bus width of the slave interface? ex) If addressblock width =16, data bus(apb_wdata, apb_rdata) width is 16. is it right?
  7. Hi, I have some question about access the register below case... [ip-xact information] - slave interface. bitInLau : 8 - addressblock width : 16 - addressUnitBits : 8 - register name A: - register offset : 0 - register size : 32 - register name B: - register offset : 1 - register size : 32 Q1) Does the above description have any problem in the ip-xact standard? Q2) In case of the above description, maximum single transfer size is 16. Because address block width is 16. Is it right? Q3) I know as below. Is it right? addr_offset@ip-xact address @ slave interface access register 0x0 0x0 A[15:0] 0x1 0x2 B[15:0] Q4) How can access the register A[31:16] ? Thanks & regards, Suhyun
  8. Hi I'm new to uvm-systemc. I previous use systemc to write some code, and I use the following code to compile it. g++ -I. -I$SYSTEMC_INCLUDE -L. -L$SYSTEMC_LIBDIR -Wl,-rpath=$SYSTEMC_LIBDIR -o hello hello.cpp -lsystemc -lm However when I looked in to uvm-systemc documents, I cannot find any of them tell me how to compile it, and the makefile contains thousands of lines, which make me overwhelmed. Could anyone tell me about it? Thanks in advance!
  9. Last week
  10. Do you have an error message or stacktrace (gdb)? 'simulation [...] crashes suddenly' is very generic and can have manifold root causes... Where do you execute the code? You can only create sc_object based elements during elaboration. But if PortElement is a plain C++ class I have no idea why it fails...
  11. Hello, I tried out your method as follows: sc_object* test_object_find = sc_core::sc_find_object(port_name); sc_core::sc_object& obj = dynamic_cast <sc_core::sc_object&>(*test_object_find); PortElement<sc_logic>* PE = new PortElement<sc_logic>(count,hierarchical_name,port_name,obj); sc_core::sc_attribute<PortElement<sc_logic>*> attr{"PortElement", nullptr}; attr.value = PE; Until here, I am capable to build and run without issue. Then when I follow up the above lines of code with this one: obj.add_attribute(attr); I can build, but when I run the simulation it crashes suddenly. Which failure did I make when adding the attribute to the port object? Thanks for your help.
  12. I guess your problem stem from a particular implementation detail in SystemC: if you have an inheritance hierarchy you should declare all constructor parameters as ' my_module( sc_core::sc_module_name const& nm). For the leaf module can leave it as 'MyModule(sc_core::sc_module_name nm)'. In the second case a copy of the module name is created which manipulates the hierarchy stack of the kernel. I assume this way you srew up your design. It is save to always pass the sc_module_name by const reference in the constructors. This would makeup for a good rule in a modleing guideline
  13. Well, sc_fifo is not TLM. For your example the basic question is: what is the protocol on fifo_out? Should it be clock-based? Valid-Ready signaling? So your queastion and example is too generic and broad. If you are looking for an example to translate from TLM2.0 to pin level of an Amba AHB protocol you may have a look here: https://git.minres.com/SystemC/SystemC-Components/src/branch/master/incl/tlm/ahb/bfm and https://git.minres.com/SystemC/SystemC-Components/src/branch/master/src/tlm_ahb_bfm_initiator.cpp as well as https://git.minres.com/SystemC/SystemC-Components/src/branch/master/src/tlm_ahb_bfm_target.cpp. They implement TLM2.0 to pin and pin to TLM2.0
  14. May I ask for a reference on how to convert tlm interface to pin interface? For example, sc_fifo_in_if<T> convert sc_out<T> #include <systemc.h> class fifo_in_tlm2pin : public sc_module { public : sc_port< sc_fifo_in_if<T> > fifo_in; sc_out<T> fifo_out; SC_HAS_PROCESS(fifo_in_tlm2pin); fifo_in_tlm2pin( sc_module_name _name ) : sc_module (_name) { } };
  15. Any comment about this issue? The issue seems to be related to the internal implementation of the SystemC kernel. So if possible, I would appreciate to get the opinion of the systemC experts about it. Thanks. Julien
  16. yes, I tried it also with cmake as it is descriped in the subfolder. For SystemC 2.3.3 all test are failing due 'segmentation fault', too.(shown in LastTest.log in the attachments). Processor type is intel i5 __LP64__ due to cmake.
  17. Have you tried using CMake installation? That usually works the easiest for me. Of course you need to install cmake (https://cmake.org/download/) and then there's a separate INSTALL guide under the SystemC cmake subdirectory.
  18. Hey again, I tested the tests from systemC 2.3.2 with the same environment. Here only one test fails: 11 - examples/sysc/2.3/simple_async/simple_async (Failed) for the makefile build and the cmake build. Thats it's output: Start SystemC Fatal: (F4) assertion failed: sem_trywait == 0 In file: /Users/kwasigroch/Downloads/systemc-2.3.2/src/sysc/communication/sc_prim_channel.cpp:195 Info: (I99) simulation aborted Expected is the output(golden.log): Here cmake copies a empty expected log file. Start SystemC I'm busy! Asked to stop at time 10 ns Info: /OSCI/SystemC: Simulation stopped by user. The dog barks before the end of simulation Program completed Regards Sören Kwasigroch
  19. Hello, I wanted to build and install SystemC 2.3.3 on a Mac Catalania. I didn't called 'make install' yet due to the issue that 22 of 22 tests are failing. I checked the logs of some of the test and saw in all files that a 'segmentation fault' got thrown before producing output. While building it only throw 2 warnings see in the attachments. My environment details: OS: Mac Catalania 10.15.5 processor: intel i5 cmake found the type: __LP64__. build tool tried: make GNU Make 3.81 and cmake 3.18.1 (Therefore it should not make a different that I didn't called gmake but make instead) CXX = Apple clang version 11.0.3 in the attachment I copied the test-suit.log For cmake build the test suit also throws segmentation faults. What I found while ruining make for cmake, it thrown two errors in run_test.cmake first line 104: string(REGEX REPLACE "^.*stopped by user.*$" "" RUN_TRIMMED_LOG ${RUN_LOG}) and line 108: string(REGEX REPLACE "^.*stopped by user.*$" "" EXPECTED_TRIMMED_LOG "${EXPECTED_LOG}") message: 'string sub-command REGEX, mode REPLACE needs at least 6 arguments total to command.' Therefore I also post the 'LastTest.log to the attachment' Did you experienced this issue? Could you suggestions how to build it in a better way? I also noticed that the install.md file for SystemC 2.3.3 has the version number systemc 2.3.2. Is this a problem? Regards Sören Kwasigroch test-suite.log WarningsDuringBuild.rtf LastTest.log
  20. Hello Suhyun, Yes you are right on Q1 and Q2. On Q2, you miss one zero. It should be 0x40001 rather than 0x4001. Best regards, Erwin
  21. Earlier
  22. Thanks Eyck. I guess I forgot to add important detail. Class ExistingDesignBase as mentioned in first version - is base for every module in design. There are about 40 modules in the design. And the top level class TlmModule, has few modules inside it. Could this lead up to any issue to sc_module hierarchy ? I observed that this message is thrown from sc_port.cpp if the check for parent of sc_module fails. Thanks
  23. AFAIK the first version should properly instantitate. Maybe you mess up within the constructor ... Since this is not really source code it is hard to tell any further. Maybe you can provide a silghtly mor concrete example e.g. on https://www.edaplayground.com/
  24. Hi, I wanted to know calculating the bus address. [information of register in IP-XACT] - base address : 0x40000 - address offset : 1 - address unit bits : 32 - salve.bitsInLau : 8 memory_map_bit_address = bit_number_in_address_block + addressBlock.baseAddress x memoryMap.addressUnitBits = (1 + 0x40000) * 32 = (1 + 262,144)*32 = 8,388,640 slave_bus_address = memory_map_bit_address / slave.bitsInLau = 8,388,640 / 8 = 1,048,580 = 0x100004 Q1) In this case, to access the register, I use the address "0x10004" is it right? If value of salve.bitsInLau is "32",slave_bus_address = memory_map_bit_address / slave.bitsInLau = 8,388,640 / 32 = 262,145 = 0x4001 Q2) In this case, to access the register, I use the address "0x4001" is it right? Thanks & regards, Suhyun
  25. Hi All, I am modifying an existing functional model for my hardware to make it cycle accurate. I get aforesaid error, for my slightly longer hierarchy of classes. class Port { tlm_utils::simple_target_socket<Port> socket_; } class Memory { Port *port; } class TlmMemory::public ExistingMemory{ Memory *mem; } class TlmModule :: public ExistingModule { TlmModule(sc_module_name nm); //socket connection is done here. tlm_utils::simple_initiator_socket<TlmModule> socket_; TlmMemory *tlmMem; } class ExistingModule :: public ExistingModuleBase { } class ExistingModuleBase :: public ExistingDesignBase { } class ExistingDesignBase :: public sc_core::sc_module { } However I do not get the error with following, however this is not what I would ideally like to do - class TlmModule :: public ExistingModule, public sc_core::sc_module { TlmModule(sc_module_name nm); //socket connection is done here. tlm_utils::simple_initiator_socket<TlmModule> socket_; TlmMemory *tlmMem; } class ExistingModule :: public ExistingModuleBase { } class ExistingModuleBase :: public ExistingDesignBase { } class ExistingDesignBase { } I would like request help about why my first method of putting sc_module at the bottom of my class hierarchy is not working. Thanks.
  26. Basically yes but just add_attribute is not enough. From the top of my head: you need to declare in your sc_module: sc_core::sc_attribute<A*> attr{"attr", nullptr}; sc_core::sc_in<bool> pin{"pin"}; in the constructor of your sc_module you need to add the attribute to the sc_object/sc_port: pin.add_attribute(attr); via attr.value = new A(); you can assign a value. This way the attribute can be found e.g. via the SystemC object tree (sc_core::sc_get_top_level_objects() ). Alternatives depend of your goal. One option would be to use CCI, esp. cci_param. But again, it depends what you want to achieve...
  27. Hello, I have defined one class "Class A" and when creating instances of that class e.g. A* instA1 = new A (); I want to attach the instA1 object to an sc_in port of my SystemC module as an attribute of that port. - Can I use for that purpose the add_attribute function? - How safe is that? - Are there any other recommended mechanisms (as alternatives)? Thanks.
  28. Thanks @Eyck @maehne and @David Black for your replies. All yours solutions and advices really help for my understanding. Thanks again 🙂 Best Regards, Nitin_S
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