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  3. My question is how to implement a GCD chip in Cascade. I've read the guide but I could not get it done. Here is my code: #include <cascade/Cascade.hpp> class GCD_core : public Component { DECLARE_COMPONENT(GCD_core); public: GCD_core(COMPONENT_CTOR) { GCD.setType(PORT_LATCH); } const char *Component_name; Input <u32> A, B; Input <bit> start; Output <bit> done; Output <u32> GCD; Clock clk; enum states{idle, compare, finish}; Signal(states, P_state); Signal(states, N_state); void reset() { done << 0; GCD << 0; P_state = idle; N_state = idle; } void update() { switch (P_state) { case idle: if (start == 1) { N_state = compare; } else N_state = P_state; break; case compare: if (A == B) { N_state = finish; done = 1; GCD << A; } else if (A > B) { A = A - B; N_state = P_state; } else { B = B - A; N_state = P_state; } break; case finish: done << 1; GCD << A; start << 0; default: N_state = idle; break; } } void archive(Archive &) {} }; class GCD_core_TB : public Component { DECLARE_COMPONENT(GCD_core_TB); public: GCD_core_TB(const char *name,COMPONENT_CTOR):Component_name(name) { DUT.clk << clk; DUT.start << start; DUT.A << A; DUT.B << B; DUT.GCD << GCD; DUT.done << done; } Input(u32, A); Input(u32, B); Input(bit, start); Output(u32, GCD); Output(bit, done); Clock clk; void reset(){} void update() { clk.generateClock(500); Sim::init(); while (1) { char buff[64]; printf("A = "); int a = (int)(fgets(buff, 64, stdin)); printf("\nB = "); int b = (int)(fgets(buff, 64, stdin)); if (*buff == 'q') break; if (*buff == 'l') { SimArchive::loadSimulation("GCD.vcd"); printf("Simulation restored from GCD.vcd\n"); } else if (*buff == 's') { SimArchive::saveSimulation("GCD.vcd"); printf("Simulation saved to GCD.vcd\n"); continue; } this->A << a; this->B << b; Sim::run(); printf("\nGCD is: %d", this->GCD); Sim::reset(); } } void archive(Archive &) {} const char *Component_name; protected: GCD_core DUT; }; int main(int csz, char ** rgsz) { descore::parseTraces(csz, rgsz); Parameter::parseCommandLine(csz, rgsz); GCD_core_TB chip("GCD_TEST"); Sim::dumpSignals(chip.Component_name); return 0; } I could not find any related forum to state my problem. So I would be grateful if anyone with Cascade experience could guide me on this.
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  5. Hi @Admin , please let me know if my theory holds water?
  6. Hi there, thanks for the post! I'm not sure where that image is from, but there's no plans to remove the runtime phases from UVM.
  7. @johannes.walter; is my_reg defined in uvm_reg_backdoor? how do I provide the reg name to this function?
  8. Hi I was planning to move my TB flow from run_phase to main_phase and other runtime phases to take advantage of these phases. But I've received the attached snapshot indicating these phases would be removed in the future UVM versions. Is this change approved?
  9. I found the issue, I was making modules in places that was not the SC_CTOR. Thanks for the help.
  10. thankyou for your replay yes i included it. it runs well on edaplayground but do not know how to setup it on Aldec Riviera-pro. it gives error there simple_component.sv
  11. In the correspondig pahse function/task you can use a `uvm_info to state in which phase you are.
  12. HI to all. I am new to UVM and Riviera-Pro. Kindly guide me/help me to setup UVM environment in Riviera-Pro 2014.10. i tried my best but still unable to run UVM in Riviera-Pro. indicating the UVM macros as undefined. Thanks in advance Kind Regards
  13. Hi to all. I am dead stuck in an issue with Riviera-Pro 2014.10 I am running a builtin example in the C:\Aldec\Riviera-PRO-2014.10\examples\systemverilog\uvm-1.2\integrated\ubus that causue an error Fatal Error: ELAB2_0036 Unresolved hierarchical reference to "me.new.this" from module "\package uvm_1_2.uvm_pkg\.\\\uvm_pkg \\uvm_component_registry#(ubus_tb_top::ubus_example_base_test) \\ \\ 0\" (module not found). I am new to Riviera-Pro and UVM and have no idea what dose it means. Kindly help me resolving this issue. thanks in advance. Kind regards to all
  14. The error message is coming from from sc_module_registery::insert(). The code has detected an attempt to add a module after the simulator has been started. It would help to see the header files, averageTB.h and HW4ece.h
  15. Hello, This may have been asked earlier but I cant find it so I am asking again. If it is already asked, please let me know the link I have two possible extensions A and B (for simplicity only). Both are derived from tlm_extension I have a module name MOD (for simplicity again). In this I am checking if extension A is attached or not. I am not checking the extension B in MOD. It is just for tracking purposes. Extension A may or may not be present. Therefore, i am making check like this A *extA; req->get_extension(ext); // tlm::tlm_generic_payload *req is the declaration if (extA == nullptr) { do ActionX } else { do ActionY } Now what is happening is while sending a request to MOD, I attach extension B. There is not extension A attached. Therefore, I think that the check if (extA == nullptr) should return true. However, this is not the case. gdb is showing extA is actually B when doing p *extA. I think this is because both A and B are derived from tlm_extension. Is there anyway, I can do a correct check so that if extension A is not present, it should extA as nullptr especially when A is not present but B is present.? Regards Moreshwar
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  17. Your question is not stupid at all, but requires knowledge of some less widely known corners of the IEEE Std 1666-2011. Typically, people constrain the word length of their data types using the template parameters, because this has the additional advantage of enforcing correct connectivity. As you noted, the port and signal types construct the value types using their default constructor. So, to configure the word lengths as required in your use case, you will have to profit from the fact that SystemC integers and vectors get their default length from the current sc_dt::sc_length_context in scope. I recommend to read up on the topic in chapter 7 of IEEE Std 1666-2011, in particular clause 7.2.3 "Base class default word length". I think this should allow you to implement all aspects of your use case.
  18. Skimming over your code snippets, I don't see a line, which would cause the error from your thread title. Try to reduce your code to a self-contained example, which exposes the problem. As the error message states, you cannot create new modules after elaboration has finished and simulation is running.
  19. Hi, I was experimenting with sc_fifo with the following producer-consumer code, my question is that why is the consumer not reading the values beyond 0? is it that the latest notification for sc_event at 1 has cancelled out the previous one at 0? how do I remedy this? do I have sc_fifo producer consumer dependent on clk edge only? sc_fifo_test(sc_module_name name😞sc_module(name),clk("clk",1,SC_SEC),f1(2),f2(2),f3(2){ SC_THREAD(generator1); sensitive<<clk.posedge_event(); dont_initialize(); SC_THREAD(consumer1); sensitive<<f1.data_written_event(); dont_initialize(); }; void generator1() { int v = 0; while(true) { wait(); f1.write(v); std::cout << sc_time_stamp() << ": generator1 writes " << v++ << " @delta cycle "<<sc_delta_count()<<std::endl; wait(1,SC_SEC); } } void consumer1() { int v = -1; while(true) { wait(); f1.read(v); std::cout << "\t"<<sc_time_stamp() << ": consumer1 reads " << v << " @delta cycle "<<sc_delta_count()<<std::endl; wait(2,SC_SEC); } } I get the following output execution phase begins @ 0 s 1 s: generator1 writes 0 @delta cycle 4 2 s: generator1 writes 1 @delta cycle 8 2 s: consumer1 reads 0 @delta cycle 9 3 s: generator1 writes 2 @delta cycle 12 execution phase ends @ 10 s 10 s: Cleanup: desctructor
  20. Hello! I am trying to run a testbench to simulate a simple averager circuit and I am not sure why I am getting this error. Other examples on the site don't seem to apply and I'd love any help or tips I can get. I am hoping its some simple syntax or ordering error that I am doing wrong. Here is what I am doing for the simulation: #include "averageTB.h" int sc_main(int argc, char* argv[]) { averageTB* myAVGTB = new averageTB("Testbench"); sc_trace_file* VCDFile; VCDFile = sc_create_vcd_trace_file("averageTB"); sc_trace(VCDFile, myAVGTB->rst, "rst"); sc_trace(VCDFile, myAVGTB->clk, "clk"); sc_trace(VCDFile, myAVGTB->start, "start"); sc_trace(VCDFile, myAVGTB->stop, "stop"); sc_trace(VCDFile, myAVGTB->inBus, "inBus"); sc_trace(VCDFile, myAVGTB->outBus, "outBus"); sc_start(2000, SC_NS); return 0; } Here is the code for the testbench that I wrote as well: #include "HW4ece.h" SC_MODULE(averageTB) { int ij; int NumOfInputs; sc_signal<sc_logic> rst, clk, start, stop, enableReg, selMux, selTri; sc_signal<sc_lv<8>> inBus, outBus; accAverage_Top* myTop; SC_CTOR(averageTB) { myTop = new accAverage_Top("Top-module"); myTop->rst(rst); myTop->clk(clk); myTop->start(start); myTop->stop(stop); myTop->inBus(inBus); myTop->outBus(outBus); SC_THREAD(resetting); SC_THREAD(clocking); SC_THREAD(main_task); SC_METHOD(display); sensitive << clk << rst; } void resetting(); void clocking(); void main_task(); void display(); };
  21. A better solution is to compile for C++11 (or later) instead, where sem_* APIs are not required.
  22. I managed to fix the problem. The root cause sem_init in sc_host_semaphore is deprecated in macOS Big Sur. So use sem_open instead will fix it.
  23. Does no-one have an idea, has this already been covered somewhere else or is my question so stupid?
  24. Hi @William Lock and all, Thanks for your instruction and I am able to build it on my macbook pro m1. However, I encounter problem with "make check" as all tests are failed. I also tried running the test in examples separately and it also failed with fault "zsh: segmentation fault ./simple_async". Do you know anything about it?
  25. Create a custom protocol and don't use address field if you don't have an address. If you do have an address but it has different requirements, then add a mandatory extension to the payload for your protocol.
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