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  3. Hello folks, I am trying to verify CAN bus on APB bus using UVM and SV, since i am new to it can you people give me pointers where shall i start from? Thanks, Sachin
  4. Using an array of class objects which have a covergroup in them, I've run into the following problems. I look for a solution which is supported by all/most simulators. This topic array seems to be a common issue, based upon web search results. ERROR TYPE0: Same coverage is recorded for both covergroups, despite option.per_instance=1 being used. # vsim -voptargs=+acc=npr # cg_fa[0] - Coverage=81.25 % # cg_fa[1] - Coverage=81.25 % ERROR TYPE1: Compile error with another simulator cg_fa[0] - Coverage=xmsim: *N,COVNSM: (File: ./testbench.sv, Line: 42):(Time: 0 FS + 0) Sampling of
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  6. Hello @sumit_tuwien, My suggestion would give you all the necessary compiler define switches necessary to build the SystemC sources included as part of your project build. Hope this helps. Regards, Ameya Vikram Singh
  7. I guess SC_USE_PTHREADS needs to be defined. Regards, Sumit
  8. Hi @AmeyaVS I am not building it, rather including these in my code base. Do you have any idea how to do in this case ? Regards, Sumit
  9. Hello @sumit_tuwien, Easiest way to get such details is by using CMake with Pthreads Configuration enabled to generate compile_commands.json. Just pick one of the SystemC source files from the JSON file for the compiler switches to build SystemC. You can find similar discussion here: https://forums.accellera.org/topic/5960-mingw-compile-issue/?do=findComment&comment=14662 Hope this helps. Regards, Ameya Vikram Singh
  10. Hello! If I import the SystemC library into my codebase instead of compiling it separately, then, is there any compiler define or switch I can turn on to use pthreads ? Regards, Sumit
  11. create a signal in the B module and bind it to the sc_export. The you create a SC_METHOD being sensitive to the sc_port. In the method you just read the port value and write it to the signal.
  12. Actually your code is a bit buggy and has some misconceptions. For your convenience I code up your example at https://www.edaplayground.com/x/CfVM Maybe you should read some books (e.g. @David Blacks 'SystemC from the ground up') or checkout some tutorials using a search engine of your choice.
  13. Your do_sum() is sensistive to A_val_in and B_val_in which means wati() finishes as soon as A_val_in or B_val_in gets data. Then you read the data using blocking read. This means the function waits until data in the fifo is available anyways. Your loop could be simplified as void sum::do_sum() { while(true) { unsigned int Sint = A_val_in.read() + B_val_in.read(); S_val_out.write(Sint); sum_finished.notify(SC_ZERO_TIME); } } and you don't need a sensitivity list at all. This can be done also in a non-blocking way: void sum::do_sum() { unsigned int A_v
  14. Earlier
  15. A question regarding the usage kill() and m_kill(); in uvm_squence_base.svh : the kill() method defined as below function void kill(); if (m_sequence_process != null) begin // If we are not connected to a sequencer, then issue kill locally. if (m_sequencer == null) begin m_kill(); // We need to drop the objection if we raised it... if (get_automatic_phase_objection()) begin m_safe_drop_starting_phase("automatic phase objection"); end return; end ...
  16. Hi, I am a beginner in SystemC. I am trying to create a small testcase to add two numbers. The inputs are defined as sc_fifo_in, and these are added to the sensitivity list for SC_THREAD. SC_THREAD process is somehow not responding to the sensitivity list Is there any way I can define the two sc_fifo_in signals (A_val_in and B_val_in) the sensitivity list of do_sum process? class sum : public sc_core::sc_module { public: SC_HAS_PROCESS(sum); sc_core::sc_fifo_in<sc_int<10>> A_val_in; sc_core::sc_fifo_in<sc_int<10>> B_val
  17. No, a bool does not provide events. More over of A is true for a longer time how often should the thread be activated? I guess what you need is a clock.
  18. Hi, Is it possible to trigger an SC_THREAD based on bool value rather than the edge? For eg: SC_THREAD(a_func) sensitive <<A a_func should be called when A = 1 (not when A transitions from 0 to 1). Is this possible? Thanks, Nithin
  19. I don't know where you got that specification, but it looks suspiciously like a university project. Also, whoever is using the word 'static' is not using the word correctly. Nor would or should that approach ever work. The diagram implies a hierarchy of SystemC modules with a cluster module containing several DME-array modules, which in turn contain DME, DMA and MemType2 modules. These could of course be modeled without the illustrated boundaries, but it would add unnecessary complication. The outermost module (Cluster module) would have one each of an initiator and target TLM-2.0 socket (NOT
  20. You also need to change the order of sc_start and trace file creation: sc_trace_file *tf=sc_create_vcd_trace_file("trace"); tf->set_time_unit(1,SC_NS); sc_trace(tf,A,"A"); sc_trace(tf,B,"B"); sc_trace(tf,O,"O"); sc_start(SC_ZERO_TIME); Afaik the kernel will not add traces once the simulation passed end of elaboration (which happens with the very first call of sc_start())
  21. Hello @omaima, You probably want to replace the following lines: with: sc_stop(); sc_close_vcd_trace_file(tf); Also, I would recommend that you go through the examples folder in the SystemC sources to try and understand various modelling techniques. Hope this helps. Regards, Ameya Vikram Singh
  22. I'm trying to create vcd file for data gate and I got on this : Info: (I703) tracing timescale unit set: 1 ns (trace.vcd) Warning: (W571) no activity or clock movement for sc_start() invocation In file: ../../../src/sysc/kernel/sc_simcontext.cpp:1742 my cod: //andh.h file #include <systemc.h> SC_MODULE(andh){ sc_in<bool> a; sc_in<bool> b; sc_out<bool> o; void and_process(){ o.write(a.read()&&b.read()); } SC_CTOR(andh){ SC_METHOD(and_process); sensitive<
  23. 1. Cluster – Is a module, which hosts various compute elements, and multiple arrays of DMEs. In this block diagram two DME-Array – each comprising of 4 DMEs is shown. Cluster is connected to multiple NoCs. Each DME-Array is connected to a NoC based on memory type that the array hosts. 2. DME – Dma and memory element. One DME differs from another in terms of size/banks, security and power characteristics (voltage, and power states) of its memory. There are specific NoC to connect DME-Arrays with specific mem type. There could be multiple NoCs, each connecting common MemType DM arrays. Two
  24. Hi David, Please find the block diagram attached. The textual description that goes with the pic, is in subsequent message. Thanks.
  25. Hi Torsten, Thanks for the confirmation of the issue. Regards, Julien
  26. Thanks it worked build succeeded ,but When I run the program I get this message
  27. Dear Julien, thanks for reporting that issue! I confirm your findings and have forwarded the issue to the SystemC LWG so that it can be fixed. I am sorry for the long delay reacting to your message due to the summer vacation period. Best regards, Torsten Maehne
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