Jump to content

All Activity

This stream auto-updates

  1. Today
  2. Nevermind, I found it in a previous release. uvm-crave-0.9-alpha/contrib/crave/src/include/crave2uvm.h
  3. Yesterday
  4. Hi, any updates to this topic ? I recently faced the same globals in memory leak detectors reports (valgrind on Linux and crtdbg on Windows) when only adding static linkage to systemc. update: I found SYSTEMC_MEMPOOL_DONT_USE=1 from other posts for suppressing it. But still interested as most recent posts here refer to potential other solution being considered.
  5. Last week
  6. Hi all, I got a question regarding RAL. Assuming there are 2 registers A and B whose width are 8 bits and 16 bits respectively and the bus width is 8 as well. The two UVM registers are created by new(name, 8, UVM_NO_COVERAGE) and new(name, 16, UVM_NO_COVERAGE) for defining their own width. Register A and B locate at address 0 and 1-2 as the address is byte aligned. An user defined register map is created uvm_reg_map my_map = create_map("my_map", 0, 1, UVM_LITTLE_ENDIAN, 1); my_map.add_reg(reg_A, 0, "RW"); my_map.add_reg(reg_B, 1, "RW"); After reg_B.write(status, 16'habcd, .pat
  7. Hello, I have installed CRAVE from github, and I have uvm-systemc 1.0 beta3 as well as systemc 2.3.3 on my machine. The UBUS example from Workshop: UVM-SystemC Randomization - Updates From The SystemC Verification Working Group (https://www.accellera.org/resources/videos/uvm-systemc-workshop-2021) included a file called "crave2uvm.h" but I cannot find where that header file is located within the crave files. Do I need this file to incorporate CRAVE into UVM-SystemC, and if so, where is this file located? I have attached one of the examples wherein #include <crave2uvm.h> i
  8. It is not possible to have a class object with both a member variable from B and member variable from C simultaneously; it is one or the other. So you can never randomize an object with both member variables. Perhaps you can show some example code of what you are thinking.
  9. Hi I have a base class in UVM from with two extended classes: A |------\ | | B. C I have two member variables in A, one of it is derived in B and one of it is derived in C. I want to randomise only the member variables in B, without randomising member variable in C. Is it possible to do that using UVM?
  10. Earlier
  11. Thanks @William Lock, for sharing your experience of building SystemC on macOS for the Apple M1 architecture. I opened an issue on the LWG’s internal tracker to update our build scripts so that it will work out of the box in the future.
  12. If you add the wait() into the inner for loop, the algorithm will be implemented using a FSMD architecture. Each sample will then take 4 clock cycles to get processed. A new sample is processed only every 4 clock cycles as well. If you want your algorithm to be pipelined, your loop needs to get unrolled. Depending on your HLS tool and your coding style, the synthesizer might automatically defer the pipeline, require some hint in form of a pragma or you’ll have to rewrite your model. Similar to classic HDLs, it helps to first imagine the structure and behaviour of the hardware, you want to
  13. Look at the SystemC implementation of convenience sockets and try to duplicate the approach in SV. The basic idea is to implement the TLM-2 methods inside the socket and then delegate the implementation via a callback. UVM does have callbacks, so I would guess this is not too hard to do (albeit slightly messy).
  14. Hello Bas I meet the same issue in uvm side, have you figure out the solution?
  15. Thanks @maehne, I think I understand the issue now. If I expect the algorithm to run in pipeline, and II = 1. I think I can add the setting in tool like Stratus, but how to achieve same thing just in simulation. (currently, I'm using Eclipse) Update: I tried to use wait() in the loop. Seems working as I will be updated at each clock cycle. Will this method impact with Stratus scheduling and optimization?
  16. Of course @(func(signal)) is going to cost more in performance than just plain @(signal).
  17. Thanks William for this, worked as a charm for me. I've made similar changes to the configure for SystemC AMS and succeeded in building it too. Too bad a google search on build systemc apple m1 doesn't point to this, would have saved me some time.
  18. Your code snippet of the tx_top::process() confirms that it gets activated once per rising edge of clock and then waits until the next rising edge of clock. All code, which gets executed in your while loop (including the function calls gets executed in the same delta cycle. It's important to be aware that tracing of signals and variables happens not upon assignment to them, but as part of the simulation cycle, i.e., a new trace value gets only recorded once there are no new events to process for the current time (because all signals have stabilised). After that, the simulator advances time to
  19. Hi @maehne and @AmeyaVS Thanks for the follow up. Here is the code snippet regarding with IO. I also attached full code as well.
  20. Hello @zidane, I would recommend the smallest example you can come up with the problem you are facing so as to give you a feedback effectively. You can use https://edaplayground.com/ for submitting the minimal example or as suggested by Dr. @maehne as a zip attachment to the post in the forum. You can also look into the historical posts in the forum discussing the similar issue. Regards, Ameya Vikram Singh
  21. A running simulation is no indication that you model follows established SystemC coding practices. The suggestions by @AmeyaVS are all valid. The code snippets, which you provided use for the moment only SystemC data types, but they don't define a module class with a ports interface and processes. Without a minimal, self-contained, and executable example exposing your issue, you are making it difficult to others to give you good feedback. Instead of pasting all the code, you can also attach a ZIP archive and keep code snippets to the parts, which you think are relevant for your problem. I reco
  22. Great, thank you. I was aware of ok_to_put(), but I think I had some confusion about how to use it in my situation. It looks like it should do what I need. Thanks!
  23. Hi @AmeyaVS I didn't paste all code (like IO and SC_THREAD) here otherwise it may become a length thread. But I think the code is structurally OK or the systemc simulation wont run. More about SC_THREAD This mac class will be called from sym_hbf_2x class. And the latter be called from tx_fir_0_1_4 which is called in tx_top cthread process().
  24. Hello @zidane, Instead of updating the original post with the details it would have been better to just post a new comment so as to read through the new information succinctly. Currently it's difficult to judge what changed between your original post and the edited one. But at a high-level I see that there are no SystemC processes involved, i.e. SC_THREAD/SC_METHOD's in your model design. Also, I don't see any interface definition of your FIR module implementation, i.e. Input/Output (I/O declarations). I would recommend going through some examples of designs implemente
  25. Hi @AmeyaVS Thanks for the response. I have update the post including more info you ask. Thanks Zidane
  26. Thank you very much for this additional Information. Yes, I've used sca_tdf::sca_de::sca_in/out to connect a sc_signal from a TLM module to a AMS module! Its good to know that there is a dynamic timestep feature for immediate callbacks in the TDF modules.
  27. Hello @zidane, How is the inst method called? What processes are you using(SC_[C]THREAD/SC_METHOD)? In the "inst" method the instance variable i goes through 0 to the value of tap and SystemC kernel only sees the final value of 4 as evident in your VCD Trace. It would be better if you can share a minimal example of what you are trying to achieve. Hope this helps. Regards, Ameya Vikram Singh
  28. I'm learning systemc at early stage, so pls forgive me if it's a stupid question. Code below is a fixed-point mac for FIR. This mac class will be called from sym_hbf_2x class. And the latter be called from tx_fir_0_1_4 which is called in tx_top cthread process(). When I dump the values into VCD, the index "i" stucks at "4". But other internal signals (like *_out) shows the for loop is running. How can I dump the accurate internal signals states into VCD? template<int in_bw, int out_bw, int tap, int coeff_bw, int mul_trunc, int acc_trunc> class sym
  29. Hi, Could someone clarify if there is a performance impact when using a function in an event control expression instead of a signal? Br, Salman
  1. Load more activity
  • Create New...