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  2. Avnita

    SYSTEM C

    Hello sir, I wrote and_gate systemc code with test bench and it got compiled, also generated simv but it shows Segmentation fault (core dumped) error. Could you please suggest me what exactly it is and how I will resolve this. #include "systemc.h" //AND gate module SC_MODULE (and_gate) { sc_in <bool> a, b; sc_out <bool> c; //Process for AND gate void and_fun() { c.write(a.read() & b.read()); } //Constructor for AND gate module SC_CTOR (and_gate) { SC_METHOD (and_fun); //process for sesitivity sensitive << a << b; } }; //Testbench for AND gate int sc_main (int argc, char* argv[]) { //testbench signals sc_signal <bool> a, b, c; sc_trace_file *tf; //module instantiation and name based connection and_gate and1 ("and_gate_and1"); and1.a(a); and1.b(b); and1.c(c); tf->set_time_unit(1, SC_NS); a = 0; b = 0; wait(); //sc_start(1.0, SC_NS); //a = 0; //b = 1; //wait(); //sc_start(1.0, SC_NS); //a = 1; //b = 0; //sc_start(1.0, SC_NS); //a = 1; //b = 1; //sc_start(1.0, SC_NS); //sc_stop(); cout << "Finished at time " << sc_time_stamp() << endl; return 0; } [root@silicon SYSTEM_C_FILES]# vi and_gate.cpp [root@silicon SYSTEM_C_FILES]# syscan and_gate.cpp [root@silicon SYSTEM_C_FILES]# vcs -sysc and_gate.cpp make: Entering directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc' if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath=/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4 -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -rdynamic -Wl,-E -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/sysc_globals.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ucli_sysc.o objs/GdI28_d.o objs/amcQw_d.o amcQwB.o objs/ivVCS_d.o SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_gate.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/libcsrc_sysc_stubs.a -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lsysctli -lbfSim -lbfCbug -lsystemc231-gcc4 -lvirsim -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_tls.o _vcs_pli_stub_.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_save_restore_new.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl ../simv up to date make: Leaving directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc' [root@silicon SYSTEM_C_FILES]# ./simv -gui Segmentation fault (core dumped)
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  5. Compiler already shown you where is the error and how to fix it. SystemC is a C++ library, you will need to learn C++ and get comfortable with g++ compiler before digging into SystemC.
  6. Avnita

    SYSTEM C

    I have written test bench for the above code (and gate) but i am getting some errors. Please guide me that how to write test bench in system C #include "systemc.h" #include "and_a.cpp" SC_MODULE (and_tb) { sc_in <sc_int <8> > a, b; sc_out <sc_int <8> > f; sc_in <bool> clk; void and_gate() { a.read(0); b.read(0); //f.write(0); wait(); a.read(1); b.read(1); //f.write(1); wait(); a.read(0); b.read(1); //f.write(0); wait(); a.read(1); b.read(0); //f.write(0); wait(); sc_stop(); } SC_CTOR (and_tb) { SC_METHOD (and_gate); sensitive << clk.pos(); } }; Output: error message: /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: candidate expects 0 arguments, 1 provided /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: error: no matching function for call to ‘sc_core::sc_in<sc_dt::sc_int<8> >::read(int)’ b.read(0); ^ /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: note: candidate is: In file included from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_clock_ports.h:31:0, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_:54, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc:2, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_.h:245, from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc.h:2, from /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:1: /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: const data_type& sc_core::sc_in<T>::read() const [with T = sc_dt::sc_int<8>; sc_core::sc_in<T>::data_type = sc_dt::sc_int<8>] const data_type& read() const ^ /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: candidate expects 0 arguments, 1 provided gmake: *** [and_tb.o] Error 1
  7. Avnita

    SYSTEM C

    Hello, Thankyou for your advice, I applied sc_main and I got this output mention below as screen shot.
  8. I would suggest to leave this up to the tool vendor. (I don't believe IP-XACT provides any guidelines around this) However I think any tool should only consider optimisation (or/and reporting errors) after all the connections (including inter-connections) have been fully resolved. Kind regards, Edwin
  9. Hi Kushi, In IP-XACT, an interconnect connects the logical port bits that are mapped in the connected bus interfaces. The direction of those logical bits does not matter. So the direction can be in on all end points, and also the component port bits mapped to these logical port bits can all have direction in. In an HDL netlist, this would translate to a net with all inputs at its ends. It depends on the netlister tool that you use whether such a net is actually generated or not. Typically your netlister tool generates a warning or error that you have undriven inputs. However, there is no semantic rule in IP-XACT that forbids undriven inputs. In order to drive such a net, it is sufficient in IP-XACT to connect it somehow to a component output port. This can be done with adhoc connections, additional bus interface connections, and/or phantom ports. This is completely free to decide depending on which IP-XACT design-style you wish to use. Best regards, Erwin
  10. Hi Kushi, The Accellera bus definitions contains files for I2C. There are two: one for I2C internal (uni-directional signals) and one for I2C external (bidirectional signals). They allow you to make direct connections from master to slave. A bus does not have to be symmetric to support direction connections. The bus definition property directConnection determines if you are allowed to make direct master to slave connections or not. Best regards, Erwin
  11. Hi Edwin, I understand your point but if both A.a and B.b map the clock signal and if we just connect A.a to B.b,should the tool connect the clock or not ? with error or without error ?. In general during interface connections, what happens to pins which has same direction on both sides ? Should tool connect them ? or left them unconnected ? with or without error/warning? Thanks Khushi
  12. Hello Kushi, Sorry, there is no official way to achieve this using IP-XACT 2009. Kind regards, Edwin
  13. Hello Kushi, I am not sure I understand why the tool would report an error? Let's say I have instance interface A.a connected to instance interface B.b and I have connected interface B.c to interface c on the top. A specifies clock signal clockA, B specifies clock signal clockB (both interface B.b and B.c map this clock signal) and interface c maps to signal clockTop. This means that clockA is connected to clockB and clockB is connected to clockTop all signals share the direction 'in' which means that clockTop drives this connection (perfectly valid and no need for phantom ports or components). Kind regards, Edwin
  14. Thanks Edwin. Currently we are in IP-Xact 2009. Is there a way to do this in 2009 ? Thanks Khushi
  15. Hi Edwin Thanks for your comment and links to ARM busdefs. I didn't understand the following Normally both clock and reset are "in" on both master and slave interfaces. So when you connect master to slave then - either the tool reports an error saying can not connect two ports with same direction - or ther tool just skip the connections with a warning and later we can do some adhoc connections In your environment, you mentioned the clock and reset physical ports are mapped in component master/slave bus interface with other protocol signals. In this case how you connect these with clock and reset driver without a phantom port ? Thanks Khushi
  16. Hello Kushi, In IP-XACT 2014 you can pass the parameters from component to design, this should enable what you require? Kind regards, Edwin
  17. Hello Khushi, Please use the following link for the latest versions of the AMBA bus-definitions: https://silver.arm.com/browse/AR500 In general I agree with the steps you highlight, our IPs are packaged mapping the clocks and resets in the interface. However I don't believe that this necessarily means that phantom ports or components would be required to be able to connect the clocks and resets for these interfaces, however care must be taken. Kind regards, Edwin
  18. Hi Erwin Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts. I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ? Thanks Khushi
  19. Hi Erwin, If I see the AMBA busdef AMBA_IP-XACT-1.4_BusDefinitions_2011_10_21\amba.com\AMBA4\AXI4\r0p0_0, I see for both ACLK and ARESETn, the presence element is required in both onMaster and onSlave Here you want to say something else ? =========================================================== To summarize my understanding regarding the clock and reset stuff. -a) We should list the clock and reset in protocol abstraction definition -b) We should set presence => optional for both clock and reset in both onMaster and onSlave -c) In component businterface, we can either map the physical clock and reset to busdef logical ports or not 1) if we map, then we should use phantom component strategy as you explained in ( https://forums.accellera.org/topic/6446-interface-mode-mirroredmaster-mirroredslave/ ) 2) if we not map, then either we connect clock and reset as adhoc or create clock and reset businterface in component and create interface connections for clock and reset (what is recommended here ??) Please let me know if my understanding is correct. Thanks Khushi
  20. Hi I have a design(top) with two instances of a subsystem(ss). In the subsystem(ss) I have an instance of a component(cmp). My design instances looks like top top.ss1 top.ss1.cmp top.ss2 top.ss2.cmp The component (cmp) is a generic component,(lets say a memory which has a generic parameter SIZE and during the instantiation of that component we specify the SIZE for that instance). I created a component and specify the SIZE as model parameter. Then I created a subsystem design with an instance of component cmp and specify the SIZE parameter in IP-Xact design(configurable element value). I instantiate that subsystem as ss1 in top. So far so good. Now I have to instantiated the same subsystem as ss2 in same top and in top.ss2.cmp.SIZE parameter value is different then top.ss1.cmp.SIZE. The cmp SIZE value is specified while creating the cmp instance in subsystem component. Here I stuck because I do not find a way to have different values of top.ss1.cmp.SIZE and top.ss2.cmp.SIZE. Is there a way to do this in Ip-Xact ? Thanks Khushi
  21. VCS invokes g++ automatically. But this is correct, sc_main is missing.
  22. mhh okay I think the problem is not pedantic, but -Wextra ... actually I use this compile options " -Wall -Wextra -pedantic", which creates warnings in clang
  23. As the error message says, you are missing the required sc_main subroutine. You did not show your invocation line, which could be helpful.
  24. @Eyck Thank you for the hint. Now that I know it, I also saw that it was done that way in the book, and I didn't spot the closing curly bracket. My overloaded sc_trace function is only matched correctly, when I don't use a ref for the TraceList argument. void sc_trace(sc_trace_file* tf, TraceList& var, const std::string& nm); // doesn't work void sc_trace(sc_trace_file* tf, TraceList var, const std::string& nm); // works Compiler output for not working case: 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\communication\sc_signal_ports.h(307): error C2665: 'sc_trace': none of the 61 overloads could convert all the argument types 1>c:\users\xx\xx\xx\milbus_cosimulator\helper.h(96): note: could be 'void sc_trace(sc_core::sc_trace_file *,TraceList &,const std::string &)' [found using argument-dependent lookup] 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(324): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const void *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(249): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxnum_fast *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(249): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxnum_fast &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(248): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxnum *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(248): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxnum &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(247): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxval_fast *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(247): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxval_fast &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(246): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxval *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(246): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_fxval &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(244): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_lv_base *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(244): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_lv_base &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(243): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_bv_base *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(243): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_bv_base &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(241): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_unsigned *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(241): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_unsigned &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(240): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_signed *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(240): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_signed &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(239): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_uint_base *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(239): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_uint_base &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(238): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_int_base *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(238): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_int_base &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(236): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_logic *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(236): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_logic &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(235): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_bit *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(235): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::sc_bit &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(232): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::uint64 *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(232): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::uint64 &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(231): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::int64 *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(231): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_dt::int64 &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(230): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const long *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(230): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const long &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(229): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const int *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(229): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const int &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(228): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const short *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(228): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const short &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(227): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const char *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(227): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const char &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(226): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned long *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(226): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned long &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(225): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned int *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(225): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned int &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(224): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned short *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(224): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned short &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(223): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned char *,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(223): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const unsigned char &,const std::string &,int)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(221): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const double *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(221): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const double &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(220): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const float *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(220): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const float &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(219): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const bool *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(219): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const bool &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(217): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_core::sc_time *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(217): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_core::sc_time &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(216): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_core::sc_event *,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\tracing\sc_trace.h(216): note: or 'void sc_core::sc_trace(sc_core::sc_trace_file *,const sc_core::sc_event &,const std::string &)' 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\communication\sc_signal_ports.h(307): note: while trying to match the argument list '(sc_core::sc_trace_file *, const T, std::string)' 1> with 1> [ 1> T=sim_type 1> ] 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\communication\sc_signal_ports.h(302): note: while compiling class template member function 'void sc_core::sc_in<T>::end_of_elaboration(void)' 1> with 1> [ 1> T=sim_type 1> ] 1>c:\users\xx\xx\xx\milbus_cosimulator\milbus_if.h(14): note: see reference to class template instantiation 'sc_core::sc_in<T>' being compiled 1> with 1> [ 1> T=sim_type 1> ] 1>c:\users\xx\xx\xx\milbus_cosimulator\milbus_if_with_model.h(14): note: see reference to class template instantiation 'milbus_if_inputs<sim_type>' being compiled 1>c:\users\xx\xx\xx\systemc-2.3.3\src\sysc\communication\sc_signal_ports.h(1144): error C2665: 'sc_trace': none of the 61 overloads could convert all the argument types With sim_type being: typedef TraceList sim_type; Why is it like that?
  25. Avnita

    SYSTEM C

    Hiiiii.........I wrote simple and gate code in system c and i am using vcs tool. could you please advice me that how do i complie this code, i follow these step to compile system c code on my tool: 1. syscan filename.cpp 2. vcs -sysc filename.cpp 3. ./simv #include "systemc.h" SC_MODULE(and_a) { sc_in < sc_uint <8> > a, b; sc_out < sc_uint <8> > f; sc_in <bool> clk; void comp_and() { f.write(a.read() & b.read()); } SC_CTOR(and_a) { SC_METHOD( comp_and ); sensitive << a << b; } }; After compilation i got this error message: Parsing design file 'csrc/sysc/simv/top.v' Top Level Modules: sYsTeMcToP sc_main TimeScale is 1 ns / 1 ps Starting vcs inline pass... 2 modules and 0 UDP read. However, due to incremental compilation, no re-compilation is necessary. if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv -m32 -m32 -rdynamic -Wl,-rpath=/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4 -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -rdynamic -Wl,-E -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/sysc_globals.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ucli_sysc.o objs/GdI28_d.o objs/amcQw_d.o amcQwB.o objs/ivVCS_d.o SIM_l.o rmapats_mop.o rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_a.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/libcsrc_sysc_stubs.a -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lsysctli -lbfSim -lbfCbug -lsystemc231-gcc4 -lvirsim -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_tls.o _vcs_pli_stub_.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_save_restore_new.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_main.o): In function `bf_main': bf_main.cpp:(.text+0x1289): undefined reference to `sc_main' /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_main': bf_deltasync.cpp:(.text+0xda2): undefined reference to `sc_main' /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_elab': bf_deltasync.cpp:(.text+0x42c9): undefined reference to `sc_main' bf_deltasync.cpp:(.text+0x4746): undefined reference to `sc_main' /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_init.o): In function `gSyscMain': bf_init.cpp:(.text+0x287): undefined reference to `sc_main' /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_scmt.o):bf_scmt.cpp:(.text+0x3c5): more undefined references to `sc_main' follow collect2: error: ld returned 1 exit status make: *** [product_timestamp] Error 1 Make exited with status 2 CPU time: .091 seconds to compile + .149 seconds to elab + .717 seconds to link Could you please advice me that how i resolve this error and is any error is there in code. Please provide some code writing skills so I can improve.
  26. This is correct, you cannot trace dynamic data structure. This is not even a SystemC limitation, but limitation of VCD waveform dump in general. VCD does not allow to add/remove signals to waveform dynamically. So usually you have two options : 1) If maximum capacity is known in advance and is small, you can create your own "list" that utilizes statically sized array as a storage: template<typename T> struct my_list_item { bool has_value = false; T value; } template<typename T, size_t MAX_SIZE> class my_list { std::array<my_list_item, MAX_SIZE> storage; // ... } 2) If maximum size is large or unknown, but it is sufficient for you to trace only head and tail of the list, you can have a copy of tail and head that is updated on every push and pop: class my_list { std::list<T> storage; my_list_item head_copy; my_list_item tail_copy; //... custom push pop }
  27. Out of curiosity, Eyck, is this actually correct/safe to do with a std::list (or std::vector or similar)? My understanding is that void sc_trace(sc_trace_file* tf, const TraceList& var, const std::string& nm); would be called once when you're calling the sc_trace for the signal/port/... carrying the TraceList, and the kernel would then keep the references to the list's elements. Now, assuming that TraceList's internal std::list would actually hold a non-constant amount of objects during the simulation, I guess you would run into the problem that the references to its members that you passed to sc_trace would be left dangling once the std::list's elements are reallocated for whatever reason (not as likely with a std::list than with a std::vector, but still a problem). Additionally, as far as I understood this, VCD's cannot deal with a varying amount of elements to be traced. So, by my understanding, the proposed method would only be safe to use if the list is known to hold a constant amount of values throughout the simulation (including during startup). I'm not sure whether SystemC's tracing mechanism can deal with a is non-constant amount of elements to be traced at all.
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