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Found 4 results

  1. *, How can I randomize with a dist and specify a weight for values not being inside a range? class randclass; rand logic [3:0] randvalue; function void post_randomize(); $display("value: %0d",randvalue); endfunction constraint inside_practice { randvalue dist { [3:4] :/ 50, !(inside {[3:4]}) :/ 50 //<--- I try to have a sort of 'others' category here }; } endclass module top; randclass randclass; initial begin randclass = new(); repeat (10) begin randclass.randomize(); end $finish(); end endmodule Reference: https://www.edaplayground.com/x/cV5 shaking off the rust after a SystemVerilog hiatus, thanks
  2. Here is a sample code of what I'm working on class c_cfg extends uvm_object; rand bit c_bit; constraint c_turnoff { c_bit == 1'b0; } ........... endclass: c_cfg 2nd file class b_cfg extends uvm_object; rand c_cfg cfg_c; ........ ........ endclass: b_cfg main file class a_cfg extends b_cfg; // I want to overwrite the constraint in c_cfg here. // I want that to be 1 endclass: a_cfg I tried overwriting the constraint in c_cfg by using the same constraint name in a_cfg, but it doesn't solve (I guess it is because in c_cfg and not in b_cfg) simulator is not able to solve the constraint. Then tried cfg_c.c_turnoff.constraint_mode(0); in the new function in a_cfg, but it still considers the constraint in c_cfg. Can someone suggest how to do that. Thanks
  3. With the following code, import uvm_pkg::*; `include "uvm_macros.svh" class seq_data extends uvm_sequence_item; `uvm_object_utils(seq_data) rand bit [7:0] addr; rand bit [7:0] data; constraint c_addr {addr >=1000;addr<2000;} constraint c_data {data >=0000;data<=4000;} function new (string name = "",uvm_component parent=null); super.new(name); endfunction virtual function void display (); `uvm_info (get_type_name (), $sformatf ("addr = 0x%0h, data = 0x%0h", addr, data), UVM_LOW); endfunction endclass class my_test extends uvm_test; `uvm_component_utils(my_test) seq_data my_data; function new(string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); my_data = seq_data::type_id::create("my_data",this); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); repeat(4) begin #10; assert(my_data.randomize()); my_data.display(); end phase.drop_objection(this); endtask endclass module top; initial begin run_test("my_test"); end endmodule I am getting the following error xmsim: *E,ASRTST (./example.sv,38): (time 30 NS) Assertion worklib.$unit_0x762d41ec::my_test::run_phase.__assert_1 has failed UVM_INFO example.sv(17) @ 30: reporter@@my_data [seq_data] addr = 0x0, data = 0x0 assert(my_data.randomize()); | xmsim: *W,SVRNDF (./example.sv,38|32): The randomize method call failed. The unique id of the failed randomize call is 3. Observed simulation time : 40 NS + 0 xmsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints: constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) xmsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints: rand variables: addr [./example.sv, 6] I am not seeing any constraint with the following expression constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) Can someone help me to understand what is going wrong here ? Thanks Khushi
  4. Yesterday, I learned that when randomize is called, all active constraints in the scope must be met ... even if you are passing a specific member as an argument to the randomize call. i.e. If you try to randomize a specific class member by passing it to the randomize call, like this: randomize(var2), all constraints in the scope of the randomize must still be met, even if they have nothing to do with the member being randomized. ***Someone please jump in if I phrased that poorly or am incorrect. In the below example there are two variables and a constraint on one. Uncommenting the line that causes the constraint on var1 to be violated will cause the later call to randomize to fail, even though it is passed an argument (var2) that has nothing to do with var1. class showit; rand int var1; rand int var2; constraint c_1 { var1<100; } endclass ////////////////////////////////////// module top; showit showit; initial begin showit=new(); //showit.var1=101; UNCOMMENT ME, PLEASE FOR FAIL as_myassert : assert(showit.randomize(var2)) begin $display("\n********** Victory : var2=%0d var1=%0d \n",showit.var2, showit.var1); end else begin $display("\n********** Defeat : var2=%0d var1=%0d \n",showit.var2, showit.var1); end end endmodule : top Pass result: ********** Victory : var2=-1424717967 var1=0 Fail result: ********** Defeat : var2=0 var1=101 I now understand randomize better. I had thought that only the constraints that pertained to the items being randomized were relevant.
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