Jump to content

UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. Is clock information allow in C with UVM testbench using DPI?

    By wilson_on,
    • 2 replies
    • 1.2k views

  2. A way of shortening uvm_info filename to ONLY filename, not path/filename?

    By aquarioz,   
    • 8 replies
    • 17.9k views

  3. In-line random variable control

    By Logger,
    • 4 replies
    • 2.1k views

  4. Hierarchical UVM Register Model and maps

    By giaco777,
    • 0 replies
    • 3k views

  5. When should we use uvm export

    By jds,   
    • 2 replies
    • 2.2k views

  6. randomize a string ?

    By ljepson74,   
    • 3 replies
    • 6.6k views

  7. Output `uvm_info to file

    By Vyacheslav,   
    • 2 replies
    • 5.2k views

  8. Coverage across multiple interfaces

    By imajeeth,   
    • 0 replies
    • 4.2k views

  9. assertion to check for an array of channels

    By ljepson74,   
    • 4 replies
    • 4.7k views

  10. walk thru an enumeration

    By ljepson74,   
    • 1 reply
    • 20.8k views

  11. Index Pool Mgmt

    By pavan.kota@sandisk.com,   
    • 1 reply
    • 1.3k views

  12. overlapped implication vs logical AND. |-> vs. &&

    By ljepson74,   
    • 3 replies
    • 2.3k views

  13. UVM -Control an interface pin from different agents

    By Hongnhattl,   
    • 1 reply
    • 1.9k views

  14. saving previous transaction values

    By avihai,
    • 1 reply
    • 3k views

  15. [RAL] Dealing with 64b/32b register write/read with same reg_model

    By ASRAJARAJAN,
    • 1 reply
    • 2.5k views

  16. SystemVerilog checkers. simulator support. usage in a UVM environment

    By ljepson74,   
    • 5 replies
    • 6.8k views

  17. Randomization of dynamic arrays

    By pushkarkumar,   
    • 1 reply
    • 6.1k views

  18. Could the interface be the type of another parameterized interface class?

    By sep_com,
    • 4 replies
    • 2.2k views

  19. Passing data in uvm_events.

    By mwolf,
    • 3 replies
    • 7.4k views

  20. Test for suspend/resume operation of a flash memory

    By Hongnhattl,
    • 1 reply
    • 1.6k views

  21. Array Assignment in Sequences

    By kaggala,   
    • 2 replies
    • 4.4k views

  22. Parameterised class sequence

    By qwerty,
    • 5 replies
    • 9.2k views

  23. randomize returns constant values

    By assafgedalia,
    • 1 reply
    • 1k views

  24. how to access verilog module internal signals in UVM testbench

    By mjet08,
    • 6 replies
    • 39.9k views

  25. functional coverage for AXI4 WREADY signal

    By debdip,   
    • 4 replies
    • 4.8k views
×
×
  • Create New...