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  1. Hi, I am trying to take instance of covergroup but unable to take it. Getting compilation instance. class model extends uvm_component; `uvm_component_utils(model) bit [2:0] state; covergroup cg_fsm_state; c1 : coverpoint state; endgroup cg_fsm_state cg_fsm_state_inst; function new(); cg_fsm_state_inst = new(); endfunctiion endclass Using above code, getting compilation error as mentioned below Error-[SE] Syntax error Following verilog source has syntax error : token 'cg_fsm_state' should be a valid ty
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