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Showing results for tags 'delay'.
The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a; always clk = #5 ~clk; always
Hello all, This is very basic question and I know its not possible, but still I need to put some delay or wait in start of simulation/end of elaboration. I will give you the background, In end of elaboration i an initializing the value to a pin, and that pin is quite required for reset vector address. In start of simulation I am opening my gdb, which which stop at my reset vector address, but it seems the gdb is not updating the reset vector value, so I need a small delay. Is it possible? Any suggestion will be very helpful :) Thanks and Regards, Nitin_s
Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
Hello, I need to port following code from Verilog to SystemC: assign #DELAY out = in; What is the best known method to do this in SystemC? Similar question on stackoverlow https://stackoverflow.com/questions/5566785/specifying-signal-delays-in-systemc-as-clause-after-in-vhdl