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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

598 topics in this forum

  1. how can we print in which phase we are in UVM

    By Serya,
    • 1 reply
    • 890 views

  2. DPI guideline for various programming language

    By Eric Hsu,   
    • 3 replies
    • 1.8k views

  3. Sft constraint vs weighted constraint

    By SV_UVM_Infant,
    • 2 replies
    • 852 views

  4. How to use a variable defined in one class into another class?

    By swapnilm,
    • 7 replies
    • 14.4k views

  5. null value when trying to get register from top reg map by get_reg_by_offset

    By Ai_Ar,   
    • 0 replies
    • 1.4k views

  6. How to access the instance ID of a class from a base_class, whose child class is instantiated inside.

    By Sujitha,
    • 0 replies
    • 452 views

  7. How do I get multiple transactions if register width is wider or narrower than bus width?

    By qurax,   
    • 0 replies
    • 1.2k views

  8. UVM randomise specific extended class only not other classes

    By Ahmad Fahad,
    • 1 reply
    • 451 views

  9. Multiple target sockets with multiple b_transport functions in one class?

    By Bas Arts,
    • 6 replies
    • 1.6k views

  10. any restrictions on expression in wait(expression)?

    By mastrick,
    • 6 replies
    • 11.2k views

  11. The question on reactive slave

    By VVdemajia,   
    • 5 replies
    • 2.7k views

  12. What happen if read access is performed on write-only register?

    By meah,
    • 1 reply
    • 2.5k views

  13. Hierarchical names in constant expression

    By Thomas Kruse,
    • 1 reply
    • 2.7k views

  14. Transaction timer expired (WDT)

    By Yan,
    • 5 replies
    • 1.5k views

  15. Printer

    By bl4ckp3rl,
    • 1 reply
    • 540 views

  16. SystemVerilog Assertions not getting included

    By Ankit Shah,
    • 2 replies
    • 612 views

  17. queue/array randomize

    By shanghai1943,   
    • 3 replies
    • 1.5k views

  18. uvm_resource_db confusion

    By shanghai1943,   
    • 2 replies
    • 1.5k views

  19. field.mirror() task not working as expected

    By shreyasraju,   
    • 7 replies
    • 5.3k views

  20. Reduction operator in case of one-bit vector

    By Thomas Kruse,
    • 2 replies
    • 982 views

  21. Array of SystemVerilog Interface

    By Thomas Kruse,
    • 2 replies
    • 3.7k views

  22. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74,   
    • 4 replies
    • 3.1k views

  23. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K,
    • 1 reply
    • 1.3k views

  24. reg.randomize doesn't work for some regs

    By Weicai,
    • 0 replies
    • 1.3k views

  25. Could not find call of check_config_usage in UVM library

    By supal,
    • 2 replies
    • 993 views
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