Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.
Public review feedback for the Security Annotation for Electronic Design Integration (SA-EDI) Draft Standard 1.0.
The SA-EDI draft standard was developed by the IP Security Assurance Working Group to address security concerns for hardware and software IP in a manner that is low-overhead, non-disruptive, and scalable across multiple target implementations. It specifies an approach to provide information about the security properties of IP; this information is relevant to the integrator and provides recommended solutions to address risks. The working group’s focus is on utilizing existing standards that pertain to IP specification, design, verification, and integration where security risk is a concern, as well as known security concerns that have been identified by either industry experience or security researchers.
The objectives of the SA-EDI standard include:
Offering IP providers a standardized means to disclose relevant security properties for the integrator to consider for integration
Assisting IP integrators in understanding and reducing security risk
Accelerating tool development to facilitate security assurance automation