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dave_59

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dave_59 last won the day on August 28 2018

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  1. I think defparam is partly to blame here. Before introducing the inline parameter override syntax using #(param1,...) in Verilog-2001, it was very difficult to predict when a parameter had received its final elaborated value relative the the module referencing it. Adding generate constructs makes that process even harder when you start allowing hierarchical references to parameters outside you instance, before the instance hierarchy has been fully elaborated. So the "no hierarchical names" rule is a broad hammer. In your particular example, you can get around this rule by using typedef in
  2. This is a open issue with the LRM. https://accellera.mantishub.io/view.php?id=7190
  3. It's not legal to dynamically select an instance of a module or interface. Elaboration flattens out all hierarchy. Arrays of instances are not true arrays like a variable. Each element could have different characteristices because of defparam, bind, and port connections. The BNF does not allow the syntax.
  4. Hi Linc, Section 4.4 Stratified event scheduler of the 1800-2017 LRM defines a time slot as A time slot is clearly a single point of time encompassing all the regions (active, inactive, nba,...) and the iteration of all the region without advancing time. A time step has a looser definition, and there is already a request to use it more consistently in the LRM. There are many uses of time step that really should be time slot. IMHO, a time step should be used to refer to a particular point in time, or the advancement from one particular time to the next nonexempt time slot.
  5. Hi Linc, Your code works correctly on three other EDAPlayground simulators.
  6. @ljepson74, All you have to do is import uvm_pkg::uvm_enum_wrapper; and you've got this handy little class to use, you don't even need to have a class based testbench.
  7. The UVM field macros do not handle OOP very well, and is one of the many reason we do not recommend using them. It would be much simpler and more efficient to use the streaming operator exactly as you wrote it in a do_pack method.
  8. The link answers the question on how to apply a distribution to any set of constraints. The dist construct only works with explicit values.
  9. https://verificationacademy.com/forums/systemverilog/distributed-weightage-constraint#reply-46525
  10. You always incur overhead for automation. Performance rapidly deteriorates as you introduce dependencies with other random variables. For example, suppose you need 8 unique values between 10 and 20. You are going be calling $urandom_range many extra times throwing away values that don't meet the constraints. And it becomes very difficult to know when there are no solutions, and you end up in infinite loops looking for solutions that are very hard to find or don't exist. This is what a constraint solver does for you. Since constraints are tied to the class inheritance system, they provide
  11. Give your error message a unique ID. Use set_report_severity_id_override to change the severity of that ID from UVM_ERROR to UVM_INFO. Then call get_id_count at the end of your test to make sure it's non-zero.
  12. The return code usually indicates successful completion of the tool and is unrelated to completion of the test. Non-zero return codes would be OS specific error codes. The SystemVerilog standard way of indicating pass/fail status is using the $info/$warning/$error/$fatal messages. Most tools are essentially catch the UVM reports and convert them to one of the SystemVerilog messages. They also have a way of detecting the most severe message issued during a run and you can use that information for determining pass/fail status.
  13. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
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