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  1. I wish to monitor two signals and wish to determine which of the two changes first and then do some work. module tb( input sel1, input sel2 ); //Determining which of the two changes first // if sel1 changed first //do some work //else //do some other work endmodule There are two signals sel1 and sel2 and I wish to monitor which of the following changed first and then do some work. Can someone help me in doing the same. Thank you.
  2. I have to not only display but write the values in a file also. I am unable to figure when to write it to the file. I am attaching a picture for the scenario. The rdata is a 32-bit value and not a single.Shown for simplicity as a single bit. See how the rdata changes between two clock pulses. How can i record that data
  3. I have to write a code that can be synthesised in verilog language and it displays a few values. I need to display the read and write data being read/written to some registers using the AHB protocol. I successfully displayed the write data but I am stuck in displaying the read data. Since the read appears after some time, I couldn't find a way to capture and display the read data. Initially I thought of this : @(negedge clk) wait(rdata) $fdisplay(rdata) But there could be multiple non-zero Read transactions. Now i am stuck here : @(negedge clk) //wait for rdata to change $fdisplay(rdata) I am new to verilog and SystemVerilog. Please help Thank you
  4. I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.
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