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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

598 topics in this forum

  1. Constrained Random Performance

    By sas73,
    • 4 replies
    • 3.6k views

  2. Functional coverage- VCS

    By vaibhav0901,
    • 3 replies
    • 7.6k views

  3. apb_master (in UVM examples) read task is having an issue

    By amg19,
    • 0 replies
    • 1.5k views

  4. Log File Parsing

    By sas73,
    • 6 replies
    • 3.9k views

  5. Verifying Verification Components

    By sas73,
    • 7 replies
    • 1.4k views

  6. Assert Macros

    By sas73,
    • 0 replies
    • 817 views

  7. RAL Backdoor write

    By ripal,
    • 2 replies
    • 2.8k views

  8. updating register value in UVM register model when DUT registers value changes internally

    By Khushi,
    • 1 reply
    • 2.3k views

  9. `uvm_do(), `uvm_create/`uvm_send vs sart_item/finish_item

    By Somasekhar,   
    • 1 reply
    • 17.6k views

  10. how to overwrite the constraint that's present in another file.?

    By aalpa23,   
    • 1 reply
    • 2.9k views

  11. assertion with delay values from array

    By qwerty,
    • 0 replies
    • 864 views

  12. Issue with clocking block output

    By Veeraraju,
    • 0 replies
    • 790 views

  13. parsing using system verilog

    By iidolevy,
    • 2 replies
    • 3.9k views

  14. uvm_reg_hw_reset_seq generates all addresses

    By Khushi,
    • 0 replies
    • 990 views

  15. string literal spanning a newline (using a backslash) - vendor supported?

    By ljepson74,   
    • 11 replies
    • 15.5k views

  16. interface module with TLM2 interface

    By Khushi,
    • 1 reply
    • 965 views

  17. UVM Error : These constraints contribute to the set of conflicting constraints

    By Khushi,   
    • 2 replies
    • 6.1k views

  18. Chnages in paylod in UVM b_transport not reflected on TLM side

    By Khushi,   
    • 0 replies
    • 766 views

  19. Any DPI which can call Python in verilog testbench?

    By wilson_on,
    • 4 replies
    • 12k views

  20. Problem while starting a UVM sequence by calling `uvm_do_on from the run_phase of uvm_test

    By Suraj Gupta,
    • 0 replies
    • 1.9k views

  21. timing of assertion disable condition (iff) - 2017 LRM

    By ljepson74,   
    • 1 reply
    • 3.7k views

  22. Sequence running on virtual sequencer

    By Upendra,
    • 0 replies
    • 1.8k views

  23. Maybe an error on UVM 1.1d for uvm_reg_map.svh class

    By joniale,   
    • 2 replies
    • 1.9k views

  24. Strength information threw nettype definitions

    By Victor,   
    • 0 replies
    • 1.1k views

  25. UVM testbench simulation using VCS in command mode

    By raiyyanfaisal09,   
    • 0 replies
    • 2k views
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