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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. Log File Parsing

    By sas73,
    • 6 replies
    • 3.7k views

  2. Verifying Verification Components

    By sas73,
    • 7 replies
    • 1.3k views

  3. Assert Macros

    By sas73,
    • 0 replies
    • 721 views

  4. RAL Backdoor write

    By ripal,
    • 2 replies
    • 2.7k views

  5. updating register value in UVM register model when DUT registers value changes internally

    By Khushi,
    • 1 reply
    • 2.3k views

  6. `uvm_do(), `uvm_create/`uvm_send vs sart_item/finish_item

    By Somasekhar,   
    • 1 reply
    • 16.8k views

  7. how to overwrite the constraint that's present in another file.?

    By aalpa23,   
    • 1 reply
    • 2.8k views

  8. assertion with delay values from array

    By qwerty,
    • 0 replies
    • 831 views

  9. Issue with clocking block output

    By Veeraraju,
    • 0 replies
    • 757 views

  10. parsing using system verilog

    By iidolevy,
    • 2 replies
    • 3.9k views

  11. uvm_reg_hw_reset_seq generates all addresses

    By Khushi,
    • 0 replies
    • 941 views

  12. string literal spanning a newline (using a backslash) - vendor supported?

    By ljepson74,   
    • 11 replies
    • 15k views

  13. interface module with TLM2 interface

    By Khushi,
    • 1 reply
    • 916 views

  14. UVM Error : These constraints contribute to the set of conflicting constraints

    By Khushi,   
    • 2 replies
    • 5.9k views

  15. Chnages in paylod in UVM b_transport not reflected on TLM side

    By Khushi,   
    • 0 replies
    • 727 views

  16. Any DPI which can call Python in verilog testbench?

    By wilson_on,
    • 4 replies
    • 11.7k views

  17. Problem while starting a UVM sequence by calling `uvm_do_on from the run_phase of uvm_test

    By Suraj Gupta,
    • 0 replies
    • 1.7k views

  18. timing of assertion disable condition (iff) - 2017 LRM

    By ljepson74,   
    • 1 reply
    • 3.6k views

  19. Sequence running on virtual sequencer

    By Upendra,
    • 0 replies
    • 1.7k views

  20. Maybe an error on UVM 1.1d for uvm_reg_map.svh class

    By joniale,   
    • 2 replies
    • 1.8k views

  21. Strength information threw nettype definitions

    By Victor,   
    • 0 replies
    • 1k views

  22. UVM testbench simulation using VCS in command mode

    By raiyyanfaisal09,   
    • 0 replies
    • 1.9k views

  23. uvm_monitor and class parameter

    By verif_learner,   
    • 0 replies
    • 1.5k views

  24. Loop over class attributes in SV/UVM

    By udmittal,
    • 0 replies
    • 1.3k views

  25. Where to implement functional coverage

    By verif_learner,   
    • 0 replies
    • 1.2k views
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