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Thomas Kruse

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  1. Because of the increasing number of parametrized designs, is there a definition for the behavior of the reduction operators in SystemVerilog if the input vector is just one bit? module reduction #( in_c = 1 ) ( input logic [in_c-1:0] i, output logic o1, o2, o3 ); assign o1 = &i; assign o2 = |i; assign o3 = ^i; endmodule Thanks Thomas
  2. Thanks a lot, Dave! Now I understand the issue. Best regards, Thomas
  3. I get an error with an array of an interface, when I try to use one single element of the array addressed by an variable index: interface single_if; logic [7:0] data_orig; logic [7:0] data_modified; modport slave ( input data_orig, output data_modified ); modport master ( output data_orig, input data_modified ); endinterface module bus_bridge #( in_p = 2 ) ( single_if.master array_if_in [0:in_p-1], input logic [$clog2(in_p)-1:0] sel, single_if.slave single_if_out ); assign single_if_out.data_modified = array_if_in[sel]
  4. In the LRM, it is stated that these example should not be considered as an assignment-like context: - a static cast - a default correspondence between an expression in an assignment pattern and a field or element in a data object or data value What is the consequence of this statement? Especially, what is the difference between the default correspondence (as a non-assignment-like context) and the nondefault correspondence (as an assignment-like context)? Thanks a lot Thomas
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