Jump to content

Thomas Kruse

Members
  • Posts

    6
  • Joined

  • Last visited

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

Thomas Kruse's Achievements

Member

Member (1/2)

0

Reputation

  1. If an IP should be designed with a parameterized interface and additional ports, which should use the same parameter, then this cannot be directly handled in SystemVerilog. So, obviously, you cannot write something like interface bus #(N = 8) (); logic [N-1:0] adr; modport send ( output adr); endinterface module m (bus.send intf0, input adr_pure1 [intf0.N-1:0]); endmodule So, the parameter has to provided twice. Unfortunately, it is even not possible to do a check at elaboration time that the values are identical. interface bus #(N = 8) (); logic [N-1:0] adr; modport send ( output adr); endinterface module m #(M = 8) (bus.send intf0, input adr_pure1 [M-1:0]); if (M != intf0.N) $error("unequal parameters"); endmodule Hierarchical names cannot be used in constant expression. Is there a good reason for this limitation? Best regards, Thomas
  2. Because of the increasing number of parametrized designs, is there a definition for the behavior of the reduction operators in SystemVerilog if the input vector is just one bit? module reduction #( in_c = 1 ) ( input logic [in_c-1:0] i, output logic o1, o2, o3 ); assign o1 = &i; assign o2 = |i; assign o3 = ^i; endmodule Thanks Thomas
  3. Thanks a lot, Dave! Now I understand the issue. Best regards, Thomas
  4. I get an error with an array of an interface, when I try to use one single element of the array addressed by an variable index: interface single_if; logic [7:0] data_orig; logic [7:0] data_modified; modport slave ( input data_orig, output data_modified ); modport master ( output data_orig, input data_modified ); endinterface module bus_bridge #( in_p = 2 ) ( single_if.master array_if_in [0:in_p-1], input logic [$clog2(in_p)-1:0] sel, single_if.slave single_if_out ); assign single_if_out.data_modified = array_if_in[sel].data_modified; // error: sel is not a constant object endmodule I've tried two tools and both do not accept sel if it is not constant. Is this a rule of SystemVerilog or just a tool limitation? I could not find any hint in the LRM that such an indexing is not valid. Best regards, Thomas
  5. In the LRM, it is stated that these example should not be considered as an assignment-like context: - a static cast - a default correspondence between an expression in an assignment pattern and a field or element in a data object or data value What is the consequence of this statement? Especially, what is the difference between the default correspondence (as a non-assignment-like context) and the nondefault correspondence (as an assignment-like context)? Thanks a lot Thomas
×
×
  • Create New...