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Showing results for tags 'assertion'.
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The below assertions check that gnt is not high for consecutive clk cycles. Q1: v1 vs. v2: Are there benefits or relevant differences between these styles. Q2: v2 vs. v3: Does the placement of delay matter? Besides for end of simulation termination. The questions are mainly about whether some style is better for the simulator, or there is some non-obvious situation I should consider. module top; bit clk, gnt; bit [19:0] gnt_a; initial begin gnt_a = 20'b0011001010_0000001101; #200 $finish; end assign gnt = gnt_a[19]; always clk = #5 ~clk; always -
I recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello Wor
