Jump to content

Search the Community

Showing results for tags 'property'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV, CRAVE, FC4SC)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM (IEEE 1800.2) - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
  • Portable Stimulus
    • Portable Stimulus Discussion
    • Portable Stimulus 2.0 Public Review Feedback
  • IP Security
    • SA-EDI Standard Discussion
    • IP Security Assurance Whitepaper Discussion
  • IP-XACT
    • IP-XACT Discussion
  • SystemRDL
    • SystemRDL Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 2 results

  1. Hi there, i'm currently building a host-compiled cpu/os simulator in systemC. I therefore have defined an OS interface like this: class OS_API : virtual public sc_core::sc_interface { public: virtual void task_create() = 0; virtual void task_end() = 0; virtual void CPU_WAIT_TIME(double t) = 0; }; And implemented it using: class RTOS : public sc_core::sc_module, public OS_API { public: sc_core::sc_export<OS_API> os_export{"os_export"}; RTOS() : sc_core::sc_module(sc_core::sc_gen_unique_name("RTOS")) { os_export.bind(*this); } private: // from OS API void task_create() override; void task_end() override; void CPU_WAIT_TIME(double t) override; }; So i use this whole interface / channel design in the Tasks, that are supposed to be scheduled. I defined the abstract task like this: enum State { waiting, ready, running }; struct TCB { sc_core::sc_event wakeup_event; int pid; State state; }; class OS_Task : public sc_core::sc_module { public: SC_HAS_PROCESS(OS_Task); OS_Task(sc_core::sc_module_name name_); sc_core::sc_port<OS_API> os{"os"}; struct TCB tcb; virtual void run() = 0; }; and then i have a subclass that actually implements the task: class Hello1 : public OS_Task { public: Hello1() : OS_Task("Hello1"){}; virtual void run() { cout << "running Task Hello1 \n"; os->task_create(); for (size_t i = 0; i < 20; i++) { os->CPU_WAIT_TIME(120); cout << "hello from 1: " << i << "\n"; } os->task_end(); } }; My question is, how can I access the callers information (OS_Task or its subclass Hello1) in the RTOS that implements the interface? Specifically i need access to the callers TCB struct so i can put it to sleep, and the be able to wake it up later (from the RTOS)
  2. How can I write the following sequence? If sequence A happens, then sequence A may not happen again until either sequence B or sequence C happens. An example of the sequences might be: sequence seqA; ($rose(A)) ##1 $fell(A); //single cycle A pulse endsequence sequence seqB; B[->1]; //B high for 1 cycle endsequence sequence seqC; (1[*10]); //10 clk cylces endsequence It is important in this question that seqA is a sequence, so that we are not just checking seqA |-> (!A throughout (seqB or seqC)) (For this simple example, after seqA, perhaps a 2 cycle pulse of A is acceptable, before seqB or seqC. So we specifically check for a 1 cycle pulse of A.) Although some auxiliary/extra code outside of the sequences and property (perhaps a small state machine) might help, I attempt to avoid extra code, to better understand SVA. One of my many failed attempts involves something like a liveness property. Is this a correct/possible approach? sequence seqA_with_buffer; (##[0:$] seqA ##1 1[*]); endsequence seqA |-> ( (not seqA_with_buffer) ##0 seqB ##0 seqC ) //edit: Now that I look at this again (after posting), I don't think the buffer is needed ... if this could be made to work Some non-working code is here: https://edaplayground.com/x/5z5n
×
×
  • Create New...