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Showing content with the highest reputation since 08/18/2020 in all areas

  1. 1 point
    Actually this is a Virtualizer specific question so you are better up contacting SNPS directly or try their SolvNet. But if you have missing symbols during link you miss to specify a library. How to solve this is a question to SNPS.
  2. 1 point
    This is not really a memory leak, but a very bad „model“ for the current implementation. I wonder if you saw any such scenario in a real model? „Canceled“ notifications like in your case will still be kept in the kernel‘s internal data structures until the notification time is reached (1ms in your case). You would pile up 999,999,999 of these canceled notifications until they are „deallocated“, each of them taking entries in the event queue and 16 bytes for the notification itself. Which is a lot of memory. I wrote „deallocated“ in quotes, because sc_event_timed uses a very simple memory pool based on a free list to reuse previously allocated structures. So even when the canceled notifications are released, they won‘t be handed back to the OS (not even at the end of the simulation) but will be kept allocated for future notifications. But they do not leak in an unintended way. If you change your example to e.g. have the same number of iterations without piling up billions of pending events, you should see a stable memory consumption: event.notify( 1, SC_NS ); event.notify( 1, SC_PS ); Hope that helps, Philipp
  3. 1 point
    David Black

    set sc_core::sc_in<bool>

    Let me start by observing that you probably don't want to initialize an input port. After all, inputs observe information from outside the module. So I will assume you mean an output port. If need be, you could change to use an sc_inout<T> port, but you might create a nasty race condition. The cleanest and most general approach is to write to the port during the start_of_simulation phase. How? Just create a override method, void sc_start_of_simulation(void), in your module. SC_MODULE( Example ) { sc_out<bool> oport{"oport"}; sc_signal<int> local_sig{"local_sig"}; void sc_start_of_simulation( void ) { oport->write( false ); // initialize an external signal via a port local_sig.write( 42 ); // initialize an internal signal } ... the rest of your module ... }; One other thing, I need to clear up a misconception: SystemC ports do not have a value despite the unfortunate presence of the overloaded operator=. The value that you are thinking comes from the port, actually comes from the channel it is connected to. In the case of sc_in<T> and sc_out<T>, the channels are specifically sc_signal<T>. Also, a channel itself is not data. Channels are vehicles for communication and synchronization. When you write to an sc_signal, you are depositing a value into an internal buffer, the future value buffer. When you read from an sc_signal, you are obtaining the value from another buffer, the current value. How and when the future value gets copied to the current value, is the subject of a deeper idea. For sc_signal channels, there used to be special method, init, but that is not standard. It is also the case that a constructor exists in the Proof-of-Concept implementation with a second constructor argument for initialization; however, this is also not yet standardized. So I would avoid either of these approaches.
  4. 1 point

    Pipeline with Stalling Example

    I'm not aware of any example so I will no be able to answer your question. But I do not see your problem. You would do it as it is done in hardware. Each stage is providing a ready signal indicating to the stage before that it can take inputs. And now the preceeding stage updates its outputs only if the ready signal of the next stage is active.
  5. 1 point
    David Black

    Clock Gating in SystemC?

    Three thoughts might be helpful for you to consider: You could of course use next_trigger() in SC_METHOD: SC_MODULE(HARD_WAY) { sc_in<bool> clock, clock_enabled; SC_CTOR(HARD_WAY) { SC_METHOD(gated_method); sensitive << clock; ... } ... void gated_method(void) { if ( clock_enabled and clock.posedge() ) { // Normal operations } else { // Wait until clock is re-enabled next_trigger( not clock_enabled ); } } The better way is to use sc_process_handle::disable() and enable() #define SC_INCLUDE_DYNAMIC_PROCESSES #include <systemc> #include <vector> using namespace sc_core; std::vector<sc_process_handle> gated; //< collect processes needing gating SC_MODULE(EASY_WAY) { sc_in<bool> clock; SC_CTOR(EASY_WAY) { SC_METHOD(gated_method); sensitive << clock; gated.push_back(sc_get_current_process_handle()); ... } void gated_method(void) { // Normal operations } ... }; // Process controlling gating void control thread(void) { ... if ( turn_off_clock ) { for( auto& process : gated ) process.disable(); } if ( turn_on_clock ) { for( auto& process : gated ) process.enable(); } ... } Above approach works on all static SystemC process types. Dynamic processes might escape. A more comprehensive and easier approach could be done if your gated processes are all submodules of a containing module. In that case, you skip the registration issue, because you can simply do a hierarchical search to collect the list of processes that need to be disabled or enabled at the time of power down/up. This approach will also capture dynamic processes.
  6. 1 point
    David Black

    Eclipse Windows with SystemC 2.3.0

    @omaima RTFM please. It's all in the README and related files. Better yet, signup and take a class from somebody.
  7. 1 point
    You can use group_of_animals_c::pre_randomize to create the array to the maximum possible size (12, given your constraint) and construct each element of the array. The array may shrink during randomization to satisfy other constraints. Something like this: function void pre_randomize(); animal_da = new[12]; foreach(animal_da) begin if(animal_da == null) animal_da=new(); end endfunction Using array reduction is the right idea to constraint the sum of animal weights. You can use a "with" clause to sum the individual animal weights. Something like this: constraint total_weight { (animal_da.sum with (item.weight)) == 100; }
  8. 1 point
    Roman Popov

    sc_port sc_export binding issue

    Than you have a typo in another place: class target : public sc_module { public: sc_export<sc_signal_in_if<bool> > in; ---- > Change to sc_export<sc_signal_inout_if<bool> > in; sc_signal<bool> sig; target(sc_module_name name){in(sig);} }; The problem is that you try to bind port and export with different interfaces
  9. 1 point
    this sounds like a bug. normally the sequence and/or items do know on which sequencer they run on *or should run on". there are a few situations where that in of is/was missing. a recent issue i remember was one where when an item was sent to a low level bfm sequencer from a virtual sequence running on a null sequencer then the sequencer info was wrong leading to similar fails.. /uwe
  10. 1 point
    A1: You can start your simulation with the +UVM_CONFIG_DB_TRACE plusarg to see messages for set(...)/get(...) in the log file. A2: You can have both use models. You can either tell the sequencer to start a sequence of a certain type by providing a type wrapper (like you did and the sequencer will instantiate it itself) or you can directly provide an instantiated sequence which you randomized/configured to your heart's desire (and the sequencer will start it). If you run your simulation with UVM_FULL (at least on the sequencer) you should see a message saying that it started the phase sequence and what type of sequence. A3: This error comes from start_item(...) when it can't figure out on which sequencer to start it. If you aren't starting any sequences yourself, the seq name there for the sequence probably comes from the phase sequence which is getting started. I assume you have some problems with your register model configuration (something like a sequencer not being set for the register map). Also, these built in register sequences need a register or a register block to know what to access. I don't see how you can pass the phase sequence a reference to either on of these without creating an instance first, setting the register field and only then setting it as a phase sequence.
  11. 1 point
    Hi, declaring a class virtual means that the class itself cannot be instanced - it must be extended. So you can't make an instance of uvm_scoreboard on its own. However uvm_scoreboard is itself derived from uvm_component. uvm_component has a constructor (new function) which needs the two arguments (name and parent). If you derive from a base class and don't write your own constructor in the derived class, then the default constructor will get called. If the default constructor is called, then the standard says (1800-2012 p145) "super.new call shall be the first statement executed in the constructor. This is because the superclass shall be initialized before the current class and, if the user code does not provide an initialization, the compiler shall insert a call to super.new automatically." When the compiler calls super.new for you automatically, it will not supply any arguments. Hence your original error message, which is telling you the call to new in uvm_component is not being given the correct number of arguments. regards Alan P.S. constructors are not virtual.
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