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David Black

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  1. Your observations are correct, but it really is not a problem. Even in Verilog you cannot do differently: // Verilog/SystemVerilog module Design( input CLK, AV, RD ); always @(posedge CLK) if ( AV == 0 && RD == 1 ) begin WriteDataOut(...); end endmodule So in SystemC: #include <systemc> using namespace sc_core; //< Simplifying bad practice SC_MODULE(Design) { sc_in<bool> CLK, AV, RD SC_CTOR(Design) { SC_METHOD(main_method); sensitive << CLK.pos(); } void main_method() { if( not AV->read() && RD->read() ) { WriteDataOut(...); } } }; Event driven simulators trigger on events, not values. In case you get distracted, here is a solution that will not work despite appearances: #include <systemc> using namespace sc_core; //< Simplifying bad practice SC_MODULE(Design) { sc_in<bool> CLK, AV, RD SC_CTOR(Design) { SC_METHOD(main_method); } void main_method() { next_trigger( CLK->posedge_event() & AV->posedge_event() & RD->negedge_event()); //< not what you might think if( not AV->read() && RD->read() ) { WriteDataOut(...); } } }; The & in the next trigger means that invocation will occur when all three events have happened; however, there is no requirement on when they occur. In other words, they won't be lined up correctly.
  2. You could use: #define SC_INCLUDE_DYNAMIC_PROCESSES #include <systemc> //... sc_signal<int, SC_MANY_WRITERS> sig; //... sc_spawn( [&](){ wait(DELAY); sig.write(VALUE); } ); See https://www.edaplayground.com/x/WjWw for an example.
  3. You can also use start_of_simulation, which is a more uniform approach (i.e., the concept works across all types of channels): SC_MODULE(tb) { //... void start_of_simulation() { int_o->write(0); } //... };
  4. Start address is the simulated address of the data that the pointer points to.
  5. Show your code please. Better: get a free account on EDAplayground.com and share your code from there.
  6. It is not correct to bind a port to another port directly except in the case of a hierarchical connection. Furthermore, there is no such thing as an input port or an output port in SystemC. Ports are simply sophisticated pointers to channel objects that provide methods for exchanging information. Some methods are directional in nature by g to heir behavior. For instance, sc_signal<int>::write(value) deposits it’s contents into memory managed by the sc_signal<int> channel.
  7. Look at the SystemC implementation of convenience sockets and try to duplicate the approach in SV. The basic idea is to implement the TLM-2 methods inside the socket and then delegate the implementation via a callback. UVM does have callbacks, so I would guess this is not too hard to do (albeit slightly messy).
  8. You did not post any error message, so it is practically impossible to answer your question. Perhaps you have run-time variables in the template parameters, which are strictly compile-time. In any case, this is not part of SystemC, but looks to possibly be part of an Intel FPGA package. SystemC identifiers generally begin with `sc_`. Consider: 1. Take your question elsewhere (e.g., Intel FPGA forum) 2. Look at the header file from whence it came and learn the C++ API from whence it came. If that does not make sense to you, then consider taking a course in C++.
  9. Have you tried the cmake approach? mkdir build; cd build; cmake ..; make; make install
  10. Could you put your example on EDA playground.com and share the link?
  11. Post your code on EDAplayground and I might have a look later.
  12. I concur with Eyck's comments. A few more thoughts: SystemC-processes are very different from OS processes. SystemC itself runs inside a single OS-thread. SystemC uses cooperative multitasking to simulate SystemC processes, which come in three flavors: SC_THREAD, SC_METHOD, and SC_CTHREAD (for synthesis). This is common among discrete event-driven simulators (e.g., Verilog, SystemVerilog, and VHDL use the same idea) Cooperative multitasking simplifies the coding a lot to make it easier for designers using these simulators. When documenting, I find it useful to keep these distinctions clear. To re-iterate: OS-processes and OS-threads are preemptive in nature. OS-threads live within the context of OS-processes. The primary distinction being that OS-threads share common resources (primarily memory). SystemC-processes live within a single OS-thread. SystemC-processes are not preemptive in nature, and must yield in order to allow other processes to run (i.e., cooperate to allow the simulation to proceed). The distinction between SystemC-processes is the manner in which they yield to each other: SC_THREAD-processes and SC_CTHREAD-processes yield by calling sc_core::wait(). SC_METHOD-processes yield by returning. When communicating between SystemC and an external OS-thread, SystemC events may only be invoked from within the context of the SystemC OS-thread. To inject an event, you may devise a primitive channel using async_request_update() to inject events via the update() method. C++11 provides an OS-agnostic library to create OS-threads, which is very handy. Keep in mind that data transfers between two processes must be carefully guarded using a proper mutex (available in C++11). I suggest you use a guarded mutex.
  13. Your problem is in the verilog because you created a race condition. Replace the $display with $strobe to see the proper settled condition of the signals. See https://www.edaplayground.com/x/9KdZ Perhaps you have not been formally trained in the semantics of event driven simulation.
  14. With some corrections, it works on EDA playground <https://edaplayground.com/x/q3Ei>. Note: You do really don't need those deleted copy-constructors, etc. Rule of zero works. Also SC_HAS_PROCESS works best inside the thread. Also works on under Ubuntu with GCC 10.0.
  15. That's an odd question since: 1. SystemC is software (C++ actually). 2. SystemC is used to model software running on hardware. So, most folks would model the hardware and use the software to validate the use cases. The next step would be to implement the hardware and then run the software on the real hardware. Some of the software used in a SystemC model would possibly be transformed into hardware (e.g., using an HLS synthesis tool such as Cadence Stratus, Siemens EDA's Catapult or Xilinx Vitis_HLS) or conventionally with RTL. Where is the software you ask? It depends on your approach to the modeling. 1. In some cases, it is represented by code inside a thread that uses calls to access TLM. In that case, the calls would need to be replaced with direct hardware access (e.g., with memory mapped accesses using a pointer). 2. In more traditional situations, the software would have been cross-compiled and run on an ISS wrapped into the SystemC model. Some companies even sell these.
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