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David Black

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  1. Yes, but you need to use a real string (not empty). Usually, the instance name matches the name of the instance itself. For example: #include "top_module.cpp" //< Real code goes in here #include <systemc> // Minimal sc_main function int sc_main(int argc, const char* argv[]) { Top_module top_instance{ "top_instance" }; sc_core::sc_start(); return 0; }
  2. David Black


    Depends on what the problem statement is. Likely as not, the test will rely on some type of SystemC ports for the inputs.
  3. You really should not use an empty string for the instance name.
  4. David Black


    This looks like homework and a trivial FSM. Most of the coding would be simple C++. Good luck!
  5. The syntax wait(), which calls void sc_core::wait(void), assumes a static sensitivity list, but you have not setup a static sensitivity list that I can see. Also, you are sending and immediate notification, which I somehow doubt you really grasp the implication thereof. You need to learn about the fundamentals of the SystemC scheduler to get this working correctly.
  6. Keep in mind that SystemC's kernel is not threadsafe. SC_THREAD and SC_METHOD processes are completely different animals than OS threads as well. You can use the async_request_update() method to interface into SystemC from the outside. From the inside you can of course stall everything in the SystemC side because it is cooperative multitasking system. In either case, you will need to use appropriately setup mutex to protect shared resources. Due to differences in the concept of time (simulated vs real), you will also likely need to use mailboxes for communication. You might also what to consider scheduling events to happen at the end of a delta cycle (ie. event.notify(SC_ZERO_TIME) or perhaps even a non-zero time in the future.
  7. @sas73 and @tymonx - Feel free to contact Accellera itself and try to argue your case, but the Accellera is a membership based standards organization and not subject to the whims of the general public. Large electronics and EDA companies depend on their experts who are assigned to work on those standards, and many significant tools and designs are based on their work. If your employer feels strongly about this topic, perhaps they will consider joining the Accellera organization in order to contribute to the discussions. Standards discussions are often long and drawn out with many inputs. Membership at the contributor level is not free because they want serious contributors and because the organization has funding needs to promote the standards.
  8. Please show your code and describe where you are simulating. The error messages are interesting, but do not completely tell the story as error messages often show up pointing to the wrong code.
  9. There is no default_time_unit in SystemC; however, the sc_clock default constructor does supply a default value of 1 ns. Be careful you don't set the time resolution larger than 1 ns, if you are going to use the default time. You could of course be more explict: sc_time clock{ "clock", 1, SC_NS }; //< assumes C++11 or better and using namespace sc_core
  10. What attributes are you modeling? Seems to me you would measure throughput and latency, but it might be meaningless if you are not modeling time. What assumptions are you making about the implementation technology? If somebody asked you to measure performance, ask them.
  11. First observation: sc_main is not a module. I would suggest you put them in a real top module; however, that is likely not the real problem. Second observation: you need to show us more code. WHat you have showns is insufficient to analyze. For example, we have no idea what the port connectivity is nor how it is connected. If you have TLM, then you need to show those aspect. We would need to see at least the contents of pe and cpu for the information you have shown.
  12. This is like an OO or C++ question. If you draw out the class diagram including the classes you are interested in and their relationships, that should answer your question. I would suggest using doxygen on your code base to see what it observes.
  13. Create an sc_vector<sc_signal<bool>, 4>, but then you have to assign and deal with four separate signals.
  14. Synthesizability rules are ultimately up to the HLS synthesis vendor, and they are definitely different between vendors. The synthesizable subset standard is simply a guideline of commonly agreed upon constructs that either clearly able to be synthesized (e.g. sc_signal) or not (e.g. new and delete). Every synthesis tool will have some variance. Please refer to your sythesis vendor's reference manual to learn their rules. If that fails, contact their support. Simulation does not guarantee synthesizability.
  15. Sc_signals are not data types. Sc_signals are channels, which represent hardware being modeled and are used as mechanisms to transport data between processes. As such, channels are only allowed to be created during the “elaboration phase” that occurs prior to simulation starting up. Also, strictly speaking, sc_port’s are not normal pointers; although, an underlying mechanism uses pointers for efficiencies sake. The operator->() is overloaded on sc_port<IF_TYPE>. You could of course create an sc_vector< sc_signal<T> >, N >, where N was a maximum of the number of signals required and then allocate specific index to each spawned process.
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