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Found 8 results

  1. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
  2. How can I check which VCS version I am using, from a Linux command line? I don't want to run a sim to find this information. I am looking for smthg like "irun -version", but for VCS. Pre-post discovery: It looks like "vcs -help", among other things, shows the compiler version. Afaik, the compiler version and simulator version are the same. Right? Normally, I wouldn't ask that, but I see/know that some tools (or subsections of tools) don't move in lock-step for versions (like simulators and waveform viewers). (Posting here because I didn't easily find this i
  3. Using VCS, I can compile and run multiple top-level modules. In the example I am running, I have a dut module and a bind-file module. The bind-file module is nothing more than: module bindfiles; bind dut pLib_dut p1 (.*); endmodule When I compile and run, I indeed see both top modules have been compiled: Top Level Modules: bindfiles dut And both run just fine as expected. Now the question: If I compile both top modules, can I run simv with just the dut module and ignore the bindfiles module? I would like to simulate both with the bindfiles and without th
  4. Does VCSCompiler for SystemVerilog provides support for assertion based system tasks like $assertvacuousoff. I have been compiling my .sv file and getting an UST error.
  5. During the compilation process, my code met two make erros: make[1]: *** No rule to make target `/proj/verif_release_ro/ovmkit_o2.1.2_u1.1b/14/uvm/src/dpi/uvm_dpi.c', needed by `uvm_dpi.o'. Stop. make[1]: Leaving directory `.../src/verif/interface/master/examples/master_b2b_test/csrc' Could anybody tell me what this problem is? Thank you very much in advance!
  6. Hi, all Does anybody know the differences between debug_all and debug_pp. When i use -debug_all option, vcs runs my test successfully, it will failed if i change -debug_all to -debug_pp. This is the error message and corresponding code: Error-[NOA] Null object access /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d/src/base/uvm_pool.svh, 307 The object is being used before it was constructed/allocated. Please make sure that the object is newed before using it. #0 in \uvm_object_string_pool#(uvm_event)::get at /EDA_Tools/synopsys/vcs_vE-2011.03/etc/uvm-1.1/uvm-1.1d
  7. Hi,experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error,but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 187
  8. Hi,experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error,but run time error appears. The code is as follows: 1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error 1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin 1870 pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}}; 1871 end 187
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