UVM_FATAL Errors

[Hash]

Hi

Iam new to UVM ,when i compile my test could see the UVM_FATAL error (as below), Can anyone help me understand on how to go about this errors?

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UVM_WARNING @ 0: reporter [bDTYP] Cannot create a component of type

'abc' because it is not registered with the factory.

UVM_FATAL @ 0: reporter [iNVTST] Requested test from command line

+UVM_TESTNAME=abc not found.

------------------------------------------------------------------------------------------------

2)Google search gave some information as below

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If the run_test() test name argument included in the top-module has not been registered in the UVM factory, or if the

+UVM_TESTNAME test name has not been registered in the UVM factory, then UVM reports this error.

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Can anyone help me with some inputs on how to fix this error?

-Thanks in advance

Edited January 22, 2013 by Hash
......

[whiteriver]

take a look at this tutorial: http://www.testbench.in/UT_00_INDEX.html

For your fatal error in specific, take a look at the 'Testcase source code' at http://www.testbench.in/UT_02_UVM_TESTBENCH.html

Your simulation will probably not run correctly if you don't fix that warning as well. Check if you called the factory registration macros for the 'abc' class and if you constructed it by calling the function 'new()' inside the class. An example is included in the above mentioned tutorial.

[Hash]

Iam still struck ,can anyone help here?

Iam working on an enhancement and nothing is changed(T/B&RTL) from the model X and to this model Y except for the scripting/infrastructure changes

The Golden model works fine with the enhanced infrastructure/scripts without any issues and dont see any UVM_FATAL .

Iam not able to understand from where is this UVM_FATAL is coming from..!

Any insights?

-Thanks in advance

Edited January 28, 2013 by Hash
.....

[ajeetha.cvc]

Check if you have `uvm_component_utils macro inserted in your "abc" test.

Ajeetha, CVC

www.cvcblr.com/blog

[Hash]

Thanks Ajeetha/Whiteriver for the suggestions, fixed the issue!

Best

Hash

Edited January 29, 2013 by Hash
.....

[imran]

Hi Hash..

 

How did you fix the issue?

Im also facing the same issue.

 

Thanks 

Imran

[Hash1]

Yes, Have fixed the issue!

[Harsha@1996]

Hi,

How did you resolve the issue@Hash

[Gauravgos]

Please check that test and sequence are added in test library and sequence library correspondingly.

[Shashvat Maurya]

hi @Hash how did you resolve this issue , currently i'm facing the same issue.

 

code link:-    https://www.edaplayground.com/x/dqXZ

 

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'apb_test' because it is not registered with the factory.
# UVM_FATAL @ 0: reporter [INVTST] Requested test from call to run_test(apb_test) not found.
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 3
# UVM_WARNING : 1
# UVM_ERROR : 0
# UVM_FATAL : 1
# ** Report counts by id
# [BDTYP] 1
# [INVTST] 1
# [Questa UVM] 2
# [UVM/RELNOTES] 1
#
# ** Note: $finish : /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_root.svh(135)
# Time: 0 ns Iteration: 0 Instance: /top
# End time: 04:35:08 on Nov 08,2023, Elapsed time: 0:00:07
# Errors: 0, Warnings: 4
Done

[bcassell]

19 hours ago, Shashvat Maurya said:

hi @Hash how did you resolve this issue , currently i'm facing the same issue.

 

code link:-    https://www.edaplayground.com/x/dqXZ

 

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type 'apb_test' because it is not registered with the factory.
# UVM_FATAL @ 0: reporter [INVTST] Requested test from call to run_test(apb_test) not found.
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 3
# UVM_WARNING : 1
# UVM_ERROR : 0
# UVM_FATAL : 1
# ** Report counts by id
# [BDTYP] 1
# [INVTST] 1
# [Questa UVM] 2
# [UVM/RELNOTES] 1
#
# ** Note: $finish : /usr/share/questa/questasim/linux_x86_64/../verilog_src/uvm-1.2/src/base/uvm_root.svh(135)
# Time: 0 ns Iteration: 0 Instance: /top
# End time: 04:35:08 on Nov 08,2023, Elapsed time: 0:00:07
# Errors: 0, Warnings: 4
Done

There are a few problems.

1. Your commandline needs: +UVM_TESTNAME=apb_test
2. apb_test doesn't extend from uvm_test
3. you put apb_test in my_pkg . You can either
   1. import all of my_pkg into your testbench
   2. remove apb_test from my_pkg (preferred option)
      1. this will also require adding my_pkg:: scoping to all of your class types & calls in apb_test