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Found 5 results

  1. Hello All, I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that: The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place. I would like to understand about the following conditions: 1) Can PENABLE toggle while PSEL is de-asserted? 2) Can PENABLE be asserted in the IDLE and/or SETUP phase? 3) Can PSEL go log in to the SETUP phase? 4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted? Thanks
  2. I am trying to design a GCD chip in SystemC using the model in the image. However, I have eliminated the subtractor and the comparator, and insert an ALU instead to have both functionalities in one module. I did not use the EOC either. Here is my code : #include <systemc.h> #include <ctime> class Register : public sc_module { public: sc_in<sc_logic> clk, reset, enable; sc_in<int> reg_in; sc_out <int> reg_out; SC_HAS_PROCESS(Register); Register(sc_module_name) { SC_METHOD(registering); sensitive << clk << reset; } void registering() { if (reset == '1') reg_out = 0; else if (clk->event() && (clk == '1')) if (enable == '1') reg_out = reg_in; } }; class Multiplexer: public sc_module { public: sc_in<int> in1, in2; sc_in<sc_logic> sel; sc_out <int> Out; SC_CTOR(Multiplexer) { SC_METHOD(muxing); sensitive << in1 << in2 << sel; } void muxing() { Out = (sel == '0') ? in1 : in2; } }; class ALU : public sc_module { public: sc_in <int> in1{ "in1" }, in2{ "in2" }; sc_out <int> out_sub{ "out_sub" }; sc_in < sc_logic > Opmode{ "Opmode" }; sc_out <sc_logic> equal{ "equal" }, greater{ "greater" }; SC_CTOR(ALU) { SC_METHOD(subtract); sensitive << in1 << in2; SC_METHOD(compare); sensitive << in1 << in2; } void subtract() { out_sub = 0; if (Opmode == '0') out_sub = in1 - in2; } void compare() { if (Opmode == '1') { if (in1 == in2) equal = SC_LOGIC_1; else if (in1 > in2) greater = SC_LOGIC_1; else greater = SC_LOGIC_0; } } }; class DataPath: public sc_module { public: sc_in <int> A{ "A" }, B { "B" }; sc_in <sc_logic> clk{ "clk" }, reset{"reset"}; sc_in <sc_logic> a_sel{ "a_sel" }, b_sel{ "b_sel" }; sc_in <sc_logic> ld_a{ "ld_a" }, ld_b{ "ld_b" }, ld_GCD{ "ld_b" }, OP_mode{"OP_mode"}; sc_in<sc_logic> sel_in1{ "sel_in1" }, sel_in2{"sel_in2"}; sc_out <int> GCD{"GCD"}; sc_out <sc_logic> AEB{ "AEB" }, AGB{"AGB"}; // A equal to B, A greater to B sc_signal<int> alu_in1{ "alu_in1" }, alu_in2{ "alu_in2" }, alu_out{"alu_out"}; sc_signal<int> regA_in{ "regA_in" }, regA_out{"regA_out"}; sc_signal<int> regB_in{ "regB_in" }, regB_out{"regB_out"}; sc_signal<sc_logic> regA_enb{ "regA_enb" }, regB_enb{ "regA_enb" }, regGCD_enb{"regGCD_enb"}; Multiplexer *muxA, *muxB, *muxRA, *muxRB; Register *RA, *RB, *RGCD; ALU *alu; SC_CTOR(DataPath) { muxA = new Multiplexer("muxA"); muxA->in1(A); muxA->in2(alu_out); muxA->sel(a_sel); muxA->Out(regA_in); muxB = new Multiplexer("muxB"); muxB->in1(B); muxB->in2(alu_out); muxB->sel(b_sel); muxB->Out(regB_in); RA = new Register("RA"); RA->clk(clk); RA->enable(regA_enb); RA->reset(reset); RA->reg_in(regA_in); RA->reg_out(regA_out); RB = new Register("RB"); RB->clk(clk); RB->enable(regB_enb); RB->reset(reset); RB->reg_in(regB_in); RB->reg_out(regB_out); muxRA = new Multiplexer("muxRA"); muxRA->in1(regA_out); muxRA->in2(regB_out); muxRA->sel(sel_in1); muxRA->Out(alu_in1); muxRB = new Multiplexer("muxRB"); muxRB->in1(regA_out); muxRB->in2(regB_out); muxRB->sel(sel_in2); muxRB->Out(alu_in2); alu = new ALU("alu"); alu->in1(alu_in1); alu->in2(alu_in2); alu->out_sub(alu_out); alu->equal(AEB); alu->greater(AGB); alu->Opmode(OP_mode); RGCD = new Register("RGCD"); RGCD->clk(clk); RGCD->enable(regGCD_enb); RGCD->reset(reset); RGCD->reg_in(B); RGCD->reg_out(GCD); /*SC_METHOD(datapath_function); sensitive << reset << a_sel << b_sel << sel_in1 << sel_in2 << ld_a << ld_b << ld_GCD;*/ } /*void datapath_function() { regA_in = (a_sel->read() == '0') ? A.read() : alu_out.read(); regB_in = (b_sel->read() == '0') ? B.read() : alu_out.read(); regA_out = (regA_enb.read() == '1' && ld_a.read() == '1') ? regA_in : regA_out; regB_out = (regB_enb.read() == '1' && ld_b.read() == '1') ? regB_in : regB_out; alu_in1 = (sel_in1->read() == '0') ? regA_out: regB_out; alu_in2 = (sel_in2->read() == '0') ? regA_out : regB_out; if (OP_mode->read() == "0") alu->subtract(); else alu->compare(); }*/ }; class Controller : public sc_module { public: sc_in <sc_logic> start{ "start" }, clk{ "clk" }, rst{ "rst" }, AEB{ "AEB" }, AGB{"AGB"}; sc_out <sc_logic> a_sel{"a_sel"}, b_sel{ "b_sel" }, ld_a{ "ld_a" }, ld_b{ "ld_b" }, ld_GCD{ "ld_GCD" }, OP_mode{ "OP_mode" }; sc_out<sc_logic> sel_ALU_in1{ "sel_ALU_in1" }, sel_ALU_in2{"sel_ALU_in2"}; enum states {idle, compare}; sc_signal <states> P_state{ "P_state" }, N_state{"N_state"}; // present and next states SC_CTOR(Controller) { SC_METHOD(next_state_gen); sensitive << start << P_state; SC_THREAD(seq_function); sensitive << clk << rst; } void next_state_gen(); void seq_function() { while(1) { if (rst == '1') P_state = idle; else if (clk->event() && (clk == '1')) P_state = N_state; wait(); } } }; void Controller::next_state_gen() { switch (P_state) { case idle: a_sel = SC_LOGIC_0, b_sel = SC_LOGIC_0, ld_a = SC_LOGIC_0, ld_b = SC_LOGIC_0, ld_GCD = SC_LOGIC_0; if (start == SC_LOGIC_1) { ld_a = SC_LOGIC_1, ld_b = SC_LOGIC_1; N_state = compare; } else N_state = P_state; break; case compare: sel_ALU_in1 = SC_LOGIC_0; sel_ALU_in2 = SC_LOGIC_1; OP_mode = SC_LOGIC_1; if (AEB == SC_LOGIC_1) { ld_GCD = SC_LOGIC_1; N_state = idle; } else if(AGB == SC_LOGIC_1) { OP_mode = SC_LOGIC_1; a_sel = SC_LOGIC_1; N_state = P_state; } else { sel_ALU_in1 = SC_LOGIC_1; sel_ALU_in2 = SC_LOGIC_0; OP_mode = SC_LOGIC_1; b_sel = SC_LOGIC_1; N_state = P_state; } break; default: N_state = idle; break; } } class GCD_ASIC : public sc_module { public: sc_in <sc_logic> clk{ "clk" }, rst{ "rst" }, start{"start"}; sc_in <int> A{"A"}, B{ "B" }; sc_out <int> GCD{"GCD"}; sc_signal <sc_logic> selA{ "selA" }, selB{ "selB" }; sc_signal <sc_logic> ALUsel_1{ "ALUsel_1" }, ALUsel_2{"ALUsel_2"}; sc_signal <sc_logic> LdRA{ "LdRA" }, LdRB{ "LdRB" }, LdGCD{ "LdGCD" }, OP_Sel{"OP_Sel"}; sc_signal <sc_logic> AEB{ "AEB" }, AGB{"AGB"}; SC_CTOR(GCD_ASIC) { DP = new DataPath("DataPath"); DP->clk(clk); DP->A(A); DP->B(B); DP->reset(rst); DP->a_sel(selA); DP->b_sel(selB); DP->ld_a(LdRA); DP->ld_b(LdRB); DP->sel_in1(ALUsel_1); DP->sel_in2(ALUsel_2); DP->OP_mode(OP_Sel); DP->AEB(AEB); DP->AGB(AGB); DP->ld_GCD(LdGCD); DP->GCD(GCD); CR = new Controller("Controller"); CR->clk(clk); CR->start(start); CR->rst(rst); CR->a_sel(selA); CR->b_sel(selB); CR->ld_a(LdRA); CR->ld_b(LdRB); CR->OP_mode(OP_Sel); CR->AEB(AEB); CR->AGB(AGB); CR->ld_GCD(LdGCD); CR->sel_ALU_in1(ALUsel_1); CR->sel_ALU_in2(ALUsel_2); } protected: DataPath *DP; Controller *CR; }; class GCD_ASIC_TB : public sc_module { public: sc_signal <sc_logic> clk, rst, start; sc_signal <int> A, B; sc_signal <int> GCD; GCD_ASIC *DUT; SC_CTOR(GCD_ASIC_TB) { DUT = new GCD_ASIC("DESIGN_UNDER_TEST"); DUT->clk(clk); DUT->rst(rst); DUT->start(start); DUT->A(A); DUT->B(B); DUT->GCD(GCD); SC_THREAD(clocking); SC_THREAD(reseting); SC_THREAD(inputing); } void clocking(); void reseting(); void inputing(); }; void GCD_ASIC_TB:: clocking() { while (true) { wait(10, SC_NS); clk = SC_LOGIC_0; wait(10, SC_NS); clk = SC_LOGIC_1; } } void GCD_ASIC_TB::reseting() { while (true) { wait(12, SC_NS); rst = SC_LOGIC_0; wait(15, SC_NS); rst = SC_LOGIC_1; wait(32, SC_NS); rst = SC_LOGIC_0; wait(); } } void GCD_ASIC_TB::inputing() { wait(2, SC_NS); start = SC_LOGIC_0; wait(20, SC_NS); start = SC_LOGIC_1; wait(20, SC_NS); //wait(); while (true) { srand(time(0)); wait(7, SC_NS); A = (int)(rand() % 256 + 1); srand(time(0)); wait(5, SC_NS); B = (int)(rand() % 256 + 1); } } int sc_main(int argc, char* argv[]) { GCD_ASIC_TB TB ("test_bench"); sc_trace_file *vcd_file; vcd_file = sc_create_vcd_trace_file("GCD_TEST"); sc_trace(vcd_file, TB.clk, "clock"); sc_trace(vcd_file, TB.rst, "reset"); sc_trace(vcd_file, TB.start, "start"); sc_trace(vcd_file, TB.A, "A"); sc_trace(vcd_file, TB.B, "B"); sc_trace(vcd_file, TB.GCD, "GCD"); sc_start(12000, SC_NS); sc_close_vcd_trace_file(vcd_file); return 0; } The problem is does not work. Could you please tell me where I am doing wrong?
  3. Hi Attached is the code for parallel to serial and serial to parallel conversion i have two problems in converter.cpp 1- count is not incrementing the value 2- Lout is not getting value of PS_reg in SPPS48 i am getting the following error ./../../SPPS48.h: In constructor 'SPPS48::SPPS48(sc_core::sc_module_name)': ../../../SPPS48.h:51:9: error: 'struct SPPS48' has no member named 'M1' ../../../SPPS48.h:51:16: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:51:16: error: expected ';' before 'SPPS' ../../../SPPS48.h:52:3: error: 'M1' was not declared in this scope ../../../SPPS48.h:60:3: error: 'M2' was not declared in this scope ../../../SPPS48.h:60:10: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:60:10: error: expected ';' before 'SPPS' ../../../SPPS48.h:69:3: error: 'M3' was not declared in this scope ../../../SPPS48.h:69:10: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:69:10: error: expected ';' before 'SPPS' convert.cpp main.cpp SPPS.h SPPS48.h
  4. Hi, I am very new to this forum, so please pardon any decorum that i may have violated. Here is the reference code : always @(posedge clk or negedge resetn) begin if(~resetn) begin for(int j=0; j<64; j++) enable_data[j] <= 1'b1; end else begin if(data_accepted) begin: ENABLE_DATA_BLOCK -> event_1; for (int k=0; k<64; k++) begin -> event_2; if (enable_data[k] && queue_pos_available[k]) begin -> event_3; enable_data [k] <=0; -> event_4; disable ENABLE_DATA_BLOCK; end end // for loop end // if(data_accepted) end // else block end // always... While running the above code in incisiv (version incisiv/15.20.016) i am facing the following issue: with all the condition being true that is data_accepted=1, enable_data[k]=1 and queue_pos_available[k]=1 enable_data[k] is not taking the assignment 0. event_3 and event_4 both are triggering. I ran the code by removing disable to break and the code ran correctly. So, i think there is a problem by using disable. I can't go with this fix as break is not synthesisable. My lint-run is not passing with the change of break. Thinking that there is a problem with the use of disable, i tried breaking the loop by setting the loop variable to its maximum value as: . . . if (enable_data[k] && queue_pos_available[k]) begin -> event_3; enable_data [k] <=0; -> event_4; k=64; // i am using blocking statement as i wanted to break the loop immediately. end . . I want to add a point that the code is running fine with VCS and modelsim simulators. If any-one can direct me of what can be the issue here, it will be of real help. Thanks for your time. Regards, Shubham verma
  5. Hello all, How would one go about leveraging UVM for ES level DUT verification? Most of the stuff from RTL still applies but how do we correctly use the driver and monitor if the DUT does not have signals, but has TLM ports/sockets. The UVM states that one agent should be used per interface, but the problem on the ESL is that there are no signals so how do we monitor TLM ports/sockets with the monitor, while the driver stimulates the DUT? How do we connect ports/exports to the driver, monitor and the DUT simultaneously? A solution without using analysis ports would be great. I've included an image for easier reference. I guess that on ES level the monitor and driver are redundant, but then the sequencer would have to send packets to a checker and the DUT simultaneously, which would require either two ports or an analysis port. Another option would be to keep everything the same as in the image and have two ports, one from the driver to the DUT, and one from the driver to the monitor and send packets simultaneously. Please state your thoughts on this.
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