shreyasraju Posted February 27, 2014 Report Share Posted February 27, 2014 Hi all, What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help. Thanks, Shreyas Quote Link to comment Share on other sites More sharing options...
uwes Posted February 27, 2014 Report Share Posted February 27, 2014 hi, a "force" will preserve the value on the reg/wire until you "release" the force. a value you just "deposit" will be overwritten by any subsequent value updates/assignments. /uwe Quote Link to comment Share on other sites More sharing options...
David Black Posted February 27, 2014 Report Share Posted February 27, 2014 I believe 'force' is intended for net types (e.g. wire) and uses the SystemVerilog 'force' statement; whereas, 'deposit' is intended for variables (i.e. var or reg types). Lookup the 'force' and 'release' statements in the SystemVerilog standard for more information. yeyifeng.yz and gary314 1 1 Quote Link to comment Share on other sites More sharing options...
yeyifeng.yz Posted June 27 Report Share Posted June 27 On 2/28/2014 at 4:44 AM, David Black said: I believe 'force' is intended for net types (e.g. wire) and uses the SystemVerilog 'force' statement; whereas, 'deposit' is intended for variables (i.e. var or reg types). Lookup the 'force' and 'release' statements in the SystemVerilog standard for more information. yes， great right！ deposit is useless to wire . but, if use debug_access+all in vcs , can success access wire Quote Link to comment Share on other sites More sharing options...
Recommended Posts
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.