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Hello All, I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that: The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place. I would like to understand about the following conditions: 1) Can PENABLE toggle while PSEL is de-asserted? 2) Can PENABLE be asserted in the IDLE and/or SETUP phase? 3) Can PSEL go log in to the SETUP phase? 4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted? Thanks
UVM Reference flow with 4 EDA tool scripts
sri.cvcblr posted a file in UVM
434 downloadsFixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro Fixed few issues in reg_models. Added Makefile targets for all 3 major EDA tools Steps to use ----------- tar xvfz uvm_ref_flow_2014.02.tgz cd run_dir make vcs make qsta make cdn make rvra