Jump to content

Recommended Posts

Posted

Hi  

 

I am getting expression and port bit size mismatch error : 

The following 8-bit expression is connected to 4-bit port "syndrome" of 
Expression: syndromesData[2][1]
The following 10-bit expression is connected to 5-bit port "syndrome" of 
Expression: syndromesData[0][1]

 

sydromeData is defined as : 
logic [FIELDS-1:0][STRIDE-1:0][P_BITS_PER_STRIDE-1:0] syndromesData;
and used something like this : 
syndrome(syndromesData[i][j]), 

 

whereas .syndrome is a port with variable bit size. 

 

Is it possible to fix this error ?  

 

thanks & warm regards, 

~ Rudresh

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...