Rudresh Posted January 20 Report Posted January 20 Hi I am getting expression and port bit size mismatch error : The following 8-bit expression is connected to 4-bit port "syndrome" of Expression: syndromesData[2][1] The following 10-bit expression is connected to 5-bit port "syndrome" of Expression: syndromesData[0][1] sydromeData is defined as : logic [FIELDS-1:0][STRIDE-1:0][P_BITS_PER_STRIDE-1:0] syndromesData; and used something like this : syndrome(syndromesData[i][j]), whereas .syndrome is a port with variable bit size. Is it possible to fix this error ? thanks & warm regards, ~ Rudresh Quote
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