Relationship between PSEL and PENABLE signals in the APB Protocol.

[P.Ksagar]

Hello All, 

I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that:

The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place.

I would like to understand about the following conditions:

1) Can PENABLE toggle while PSEL is de-asserted?

2) Can PENABLE be asserted in the IDLE and/or SETUP phase?

3) Can PSEL go log in to the SETUP phase?

4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted?

 

Thanks

[David Black]

This is a question for Arm and is not appropriate for UVM discussions. Please go to developer.arm.com to find your answers. We want this forum to remain focused.