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Hello All, I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that: The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place. I would like to understand about the following conditions: 1) Can PENABLE toggle while PSEL is de-asserted? 2) Can PENABLE be asserted in the IDLE and/or SETUP phase? 3) Can PSEL go log in to the SETUP phase? 4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted? Thanks
Compiling SystemC on ARM
Matthias Jung posted a topic in SystemC LanguageIn the context of the gem5 project we discovered that compiling SystemC does not work on ARM 64 bit (i.e. aarch64 has 64 bit longs). It can be fixed by adding this: https://gem5-review.googlesource.com/c/3462/1/ext/systemc/src/sysc/datatypes/int/sc_nbdefs.h Thank you and regards Matthias
SystemC for virtual prototype ARM based SOC
Anshul posted a topic in SystemC LanguageHi All, I am new to systemC and want to develop a virtual prototype for SOC, This SOC uses ARM processors and some other processors. Please provide any links/pointers to understand how to implement this virtual prototype and test each module 1. As it is required to add ARM processor IS , whether we can get complete prototype [SystemC based] (open source)] of ARM including instruction set/GIC 2. Is there any open prototype [systemC based] for DDR which can be interfaced 3. Need to install and run linux on SOC Please share some pointers for same Thanks & Regards, Anshul Kundra