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  1. Hi I was planning to move my TB flow from run_phase to main_phase and other runtime phases to take advantage of these phases. But I've received the attached snapshot indicating these phases would be removed in the future UVM versions. Is this change approved?
  2. Version version 1.11.1

    4,058 downloads

    UVM-ML Open Architecture - version 1.11.1 Enabling Multi-Language and Multi-Framework Verification Jan, 2020 General Overview Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies. This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license. This distribution includes the following main elements Backplane implementation and API Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC) Several demos and high level examples (showing all frameworks interacting) and a few smaller feature examples (tests) Docs directory with a Reference manual, User Guide and reference HTML docs Information on all news and features can be found in the ml/docs/ directory. This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. Please read the “Status, Use, and Disclaimers” section below for full details. Where to Find Information Where to start reading: point your web browser to ml/README.html The landing page provides links to installation directions, release notes, user guide, and more. For feedback or questions: send email to support_uvm_ml@cadence.com An easy installation and Setup video guide is available You can checkout the update of David I. Long form Doulos at DVCon 2016 in the US. It relates to UVM-ML (along with other updates). Blog series: Multi-Language Verification Environment—Getting First Run in Few Minutes Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi-Language Environment Multi-Language Verification Environment (#4)—Multi-Language Hierarchy Debugging Multi-Language Verification Environments UVM-ML- Managers’ Freedom of Choice Platforms and Simulators This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages. ------------------------------------------------------------------------------------------------------- UVM-ML Open Architecture: Status, Use, and Disclaimers This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution. The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact support_uvm_ml@cadence.com Use and Disclaimers: Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom). Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected. Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes. Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released. The user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed. Standardization: This package is not a standard. However, it is available as open source to all potential users. Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed. Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs. ------------------------------------------------------------------------------------------------------- What's new in each version For the full listing and more details please see the release-notes.txt file at the top of the release package. Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes. 1.11.1 Compatible with Xcelium 2021.03 (with CXX11 ABI) g++ 9.3 and CXX11 ABI (-D_GLIBCXX_USE_CXX11_ABI=1) are now supported. install*.csh now accept --use-cxx11-abi / --no-use-cxx11-abi. This sets UVM_ML_ABI_CXXFLAGS behind the curtains, respectively to -D_GLIBCXX_USE_CXX11_ABI=1 and -D_GLIBCXX_USE_CXX11_ABI=0. UVM-ML no longer interferes with uvm_objection::set_propagate_mode. When using with Xcelium, a proper warning should now be issued if both the command line "-uvmtop/-uvmtest" and uvm_ml_run_test parameters are provided. UVM-SC adapter code was reworked to avoid unnecessary thread spawning, thus improving performance and avoiding crashes in some cases 1.11 Support for calling uvm_ml_run_test() from SV program block (instead of a SV module) is now added. Note that this means that UVM Runtime phases are now blocking by default on procedural runs. Please refer to the documentation of uvm_ml_run_test() for more details. For OSCI users: "sc_simcontext::co_simulate" ML enabler is dropped, sc_start is used instead. This helps ensuring that the SystemC callbacks are separated for static vs quasi-static entities Enhanced error handling Enhanced examples- the options to run examples for multi steps with xrun and also bitness are now supported (see demo.sh -help ). 1.10.2 Supporting TCL 8.6 as of Xcelium 18.11 1.10.1 Fully qualified with IES version 15.2 and Xcelium 17.10-18.09 (the earlier version:1.10 has an issue with 18.09, which is fixed in this version). Questa 10.6b is supported 1.10: Fully qualified with IES version 15.2 and Xcelium 17.04-18.03. ASI (OSCI) 2.3.2 is supported. Support for OSCI 2.2 was dropped. Open source version can be accessed by pre-processor macros (SystemC only: UVM_ML_CURRENT_NUMERIC_VERSION and UVM_ML_NUMERIC_VERSION) or by a method (get_numeric_version) Enhancements and fixes in event propagation between frameworks Improved error handling Other fixes 1.9: Fully qualified with IES version 15.2 and Xcelium 17.04-17.10. In order to make it work with Xcelium 18.03, you can just comment the patch header in ml/adapters/uvm_e/sn_uvm_ml.e. Runtime phase synchronization between UVM-e to UVM-SV is now supported in UVM-ML OA (only with Xcelium 17.10). System C TLM2 convenience sockets (including passthrough_initiator/target_socket) are now supported by UVM-ML OA. 1.8 Fully qualified with IES version 15.2 and Xcelium 16.11-17.04. New debug command for tracing serialization in SV and e : uvm_ml trace_ser Moving from one Xcelium agile version to the other requires reinstallation of UVM-ML (running install_xclm.csh again) against the respective version) and no additional manual steps are needed 1.7: Fully qualified with IES version 15.2 and Xcelium 16.11-17.02. New debug command for observing matching types was added: "uvm_ml print_type_match". Support for multiple ML connections for SystemC TLM2 sockets. 1.6: Fully qualified with IES versions 14.2,15.1 and 15.2. UVM-SV 1.2 is now fully supported (please read RELEASE_NOTES.txt under ml directory for more details). When working with Incisive 15.2, the user can take some steps in order to skip compiling the e part of the adapter (this might be important for users that compile other e code on top of Specman, like VIP). The steps are documented in the UVM-ML OA user guide under: "Linking the Specman UVM-e Adapter From Incisive Version 15.2 On". OSCI 2.3.1 is now supported instead of OSCI 2.3, meaning that the supported OSCI versions are: 2.3.1 and 2.2. gcc 4.8.3 is now supported 1.5.1: Fully qualified with IES versions 14.1,14.2 and 15.1. Early adopters UVM-SV 1.2 support for IES (please read RELEASE_NOTES.txt under ml directory for more details). UVM-ML tcl commands are now available from Specman with all supported simulators. UVM-ML tcl commands are renamed (they all start with uvm_ml prefix, followed by a space and the command name, e.g uvm_ml print_tree). The old names are still supported. Pre-compiled UVM-SC parts for IES were eliminated. Examples are enhanced and extended. Updated the Backplane API version number. New debug commands in IES to print the UVM-ML tree, port connections, and port registrations. Brand-new documentation including User Guide, Reference Manual and more. Support for IES reset in UVM-ML environment. Support for sharing uvm_events and uvm_barriers between UVM-SV and UVM-SC. Support for +UVM_TESTNAME in all simulators and languages. Passing tlm_generic_payload transactions via analysis ports. Several ASI SystemC enhancements: Automated synchronization, ML-registering of SC TLM2 sockets. Reorganized examples to make them more useful. Enhanced and simplified installation and setup. 1.5: Fully qualified with IES versions 13.2, 14.1, and 14.2. "Phase Debug" feature, for setting breakpoints at the beginning or end of UVM-ML phases (see the Integrator User Guide for details). Currently this works only for IES. Added support for the generic UVM SV syntax, uvm_config_db#(T), so that it now works also for ML configuration Improved the way to run the demo examples and to learn how to run UVM-ML Reduced the amount of ML enabling modifications introduced into the local version of UVM-SV (1.1d), by enhancing the UVM-SV adapter implementation 1.4.4: The e macro uvm_ml_stub_unit now directly sets unit attributes hdl_path() and agent(), thus saving the user a need to add auxiliary string fields Improved the handling of UVM-ML bitness (once users select 32 or 64 bit mode, the library and all examples will run in that mode) Enhanced sequence layering capabilities Enhanced the test_env.csh script to provide more validity testing of the user's environment and to provide better suggestions how to fix issues irun_uvm_ml.*.f option files were reorganized (including a name change): IES irun invocation options were grouped into several option files, reflecting the usage context, and adding comments to clarify their meaning This release might require some changes on the user's code while upgrading to this version, see details in the release_notes.txt” 1.4.2: Fully qualified with IES version 14.1 Enables usage of Cadence UVM extensions on top of UVM-ML OA Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated Eliminated the UVM SV warnings Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly 1.4.1: New examples showing basic TLM communication Default installation is 32bit instead of 64bit Setup and install scripts renamed UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well. Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks) Methodology and examples for sequence layering across languages Enhancements in how unified hierarchy works 1.4: Support for uvm-1.1d (in place of uvm-1.1c) Addition of a portable UVM-SC adapter. Simulator independent and tested to run on several simulators Architected to be highly modular and extensible A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies) Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC Enables creating a unified hierarchy of components of different frameworks 1.2.2: Multi-Language configuration Support of TLM1 and TLM2 communication between all the provided frameworks Enhanced synchronization of test phases and delegation of phasing control to a designated framework
  3. Hi, I have a top level reg map set up as below. In my adapter I am trying to retrieve all the registers by address of incoming reg_item in bus2reg function to simulate burst condition. The get_reg_by_offset call returns null every time. I don't understand why the address is not found considering all the registers have unique offsets. Infact I retrieved the base address of the incoming reg_item to check if I can the register before incrementing for next offset, but it cannot find the register with base address. Any help is appreciated. Top register file: TOP_map = create_map(.name("TOP_map"), .base_addr('hFE00), .n_bytes(1),.endian(UVM_LITTLE_ENDIAN),.byte_addressing(1) ); default_map = CONTROL_TOP_map; TOP_map.add_submap(this.int_reg_blk.I2C_INT_map, .offset(8'h7C)); TOP_map.add_submap(this.scan_blk.SCAN_CTL_map, .offset(8'h84)); TOP_map.add_submap(this.ctrl_int_reg_blk.HOR_CTRL_map, .offset(8'h94)); TOP_map.I2C_INT_map.add_hdl_path("********", "RTL"); //didn't want to add proprietary code paths get_reg_by_offset call uvm_reg_item in_item = get_item(); base_addr = in_item.map.get_base_addr(); if(!(in_item.map.get_reg_by_offset(base_addr))) `uvm_error(get_type_name(), "Register not found in reg map") else registers[i] = in_item.map.get_reg_by_offset(base_addr+1);
  4. Hi all, I got a question regarding RAL. Assuming there are 2 registers A and B whose width are 8 bits and 16 bits respectively and the bus width is 8 as well. The two UVM registers are created by new(name, 8, UVM_NO_COVERAGE) and new(name, 16, UVM_NO_COVERAGE) for defining their own width. Register A and B locate at address 0 and 1-2 as the address is byte aligned. An user defined register map is created uvm_reg_map my_map = create_map("my_map", 0, 1, UVM_LITTLE_ENDIAN, 1); my_map.add_reg(reg_A, 0, "RW"); my_map.add_reg(reg_B, 1, "RW"); After reg_B.write(status, 16'habcd, .path(UVM_FRONTDOOR)), I would expect 2 transactions with 8 bits each appearing on the bus. However, there is only one access of h'cd to address 1. The other one never comes and it ends up throwing an error "There are 1 incomplete register transactions still pending completion" which is caused by a check on outstanding register accesses pending in predictor in check phase. I tried to find out how the original data value in uvm_reg_item gets split in reg2bus() function. It seems correct that the original data in uvm_reg_item is h'abcd and split to h'cd in uvm_reg_bus_op. But again the other part of data does not come. Also tried to search for answer from other places, for instance the same issue here https://verificationacademy.com/forums/uvm/how-handle-registers-are-wider-bus, it didn't help much unfortunately. If you have any clue about this, please leave your comments. Thanks.
  5. Why the one need to set rand variables in configuration classes ,,, my knowledge is that Virtual Sequencer is the only component whose responsibility to generate random variables, isn't it ?
  6. We are glad to open our popular, free #UVM JDI eBook for instant download now starting from 1-Jan-2021 via: https://tinyurl.com/uvmpdf Thanks to Ajeetha Kumari , Ben Cohen Shankar Hemmady and many more who inspired us to get there! No sign-ups, direct download link. It is intended for first-time #UVM learners Happy New Year 2021!
  7. What is the difference between "uvm sequence library" and "virtual sequence" ? Are these same in usage or different ?
  8. I am trying to verify 8 bit RW registers and in some of the registers 4 bits are RESERVED lets say [3:0] . My bit bash sequence tries to write in these constant bit and flags me a mismatch error in the DUT and Mirrored Value. How do i stop my bit bash sequence from checking these RESERVED bits of a register. Thanks for your help
  9. To All Design and DV Engineers! Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. There are some limitations on side of assertion cover properties but rest it compile complete SV and UVM including constraints and randomization. Learning UVM without hands-on is difficult. I believe this is opportunity for students, engineers and hobbyists to skill up without relying on paid or online tools as now you can run UVM on your system. For getting started, even though there are many UVM generators, I believe the starters need simple easy to use UVM generator tool. I found the ones available online like Easier UVM or UVMF quite difficult to use and even interact with. I developed a open-source tool "tbengy" to generate a UVM TB and Makefile that will readily get you started and will run on Vivado Simulator. You can read the instructions on https://github.com/prasadp4009/tbengy Hope it helps you all!
  10. Hello All, Please tell me the difference between transaction class and uvm_sequence_item class? Please provide me the clarity on the get_sequence_id method in uvm_sequence_item class Please provide me the clarity on the accept_tr , end_tr, start_tr in uvm_transaction class
  11. Hi, I know this will sound weird, but I will ask anyway :D I have recently completed my first ASIC design(Front end and functional verification). Although I used some SystemVerilog constructs like functions and tasks and some other stuff, but really I verified whole digital part without UVM. My question is: What are the advantages of UVM, and why UVM is needed in the first place, as it seems that tasks and functions can verify any design(it seems only, but I am not so much experienced). Will learned members shed some light on it? Thanks in advance and best wishes in fight against Corona
  12. I am new to UVM and SystemVerilog. For an effective debugging, I wanted to log my transactions coming from the DUT to the monitor into a text file. Since monitor converts into the transaction format, it becomes easy to log the transactions from monitor but I could not find a workaround to do this task. Can someone help with a solution to this problem? Currently, i am using the AHB protocol and I need to keep track of those AHB transactions coming from the DUT. I need to record the address, Read/Write, count, Data to be read/written and time stamps.
  13. Hi Team , import uvm_pkg::*; class hello extends uvm_transaction; rand bit [31:0]b1; rand bit [31:0]b2; `uvm_object_utils_begin(hello) `uvm_field_int(b1, UVM_PACK) `uvm_field_int(b2, UVM_PACK) `uvm_object_utils_end function new(string name = ""); super.new(name); endfunction endclass typedef struct {rand int s; rand int s3;}ss; class par extends uvm_transaction; function new(string name = ""); super.new(name); endfunction rand bit [31:0]s1; rand bit [31:0]s2; ss se; rand hello h1; endclass class par1 extends par; `uvm_object_utils_begin(par1) `uvm_field_int(s2, UVM_PACK) `uvm_field_int(s1, UVM_PACK) `uvm_field_int(se.s, UVM_PACK) `uvm_field_object(h1, UVM_PACK) `uvm_field_int(h1.b1, UVM_PACK) `uvm_field_int(h1.b2, UVM_PACK) `uvm_object_utils_end function new(string name = ""); super.new(name); endfunction endclass module top; par1 p; bit [7:0]que[]; initial begin p = par1::type_id::create("p"); p.randomize(); p.pack_bytes(que); //p.s1 = 3; p.s2 = 4; $display("%h, %h", p.s1, p.s2); //que = {p}; $display("%p", que); //$display("%p", p); //que = p; //que = {<<8{new(p)}}; end endmodule I want to pack in form of bits in below format que = {<<8{p.s2, p.s1, p.se.s, h1.b1, b2}} How do i achieve this..?? // que = {<<8{p.s2, p.s1, p.se.s}} //this one is working using uvm field macros. but when i add h1.b1 and h1.b2 which are sub class variables it is not working. How do i acheive this.?
  14. Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.
  15. Hi, How to handle memories wide 8 bits in my register model when register map is built with 32 bits width? Thank you Kristina
  16. In my testbench I have two background sequences (call them S1 and S2) perform register access and a test that has multiple threads ( call them T1 to T7) also performing register access on the same shared bus. T1 through T7 need to lock the sequencer in order to perform multi-cycle transactions on the CPU bus. The scenario is S1 issues a write, resulting in arb_sequence_q.size == 1 and arb_sequence_q[0].request == SEQ_TYPE_REQ in the same simulation tick, T1 through T7 issue lock requests. arb_sequence_q.size() == 8 and arb_sequence_q[0] is still the S1 request S2 issues a read, resulting in arb_sequence_q.size() == 9, arb_sequence_q[8].request == SEQ_TYPE_REQ The CPU driver calls get() and the request at the head of arb_sequence_q (the write from S1) gets popped, resulting in arb_sequence_q.size() == 8 and arb_sequence_q[0:6].request = SEQ_TYPE_LOCK and arb_sequence_q[7].request == SEQ_TYPE_REQ (this is the request from S2). finish_item is called for the S1 request, resulting in grant_queued_locks getting called, pushing all LOCK requests onto the lock_list and leaving only S2 on the arb_sequence_q. arb_sequence_q.size() == 1, arb_sequence_q[0].request = SEQ_TYPE_REQ (this is the S2 request) lock_list.size() == 7 arb_completed.num() == 0 T1 calls write, enqueuing a SEQ_TYPE_REQ on the arb_sequence_q. The arb_sequence_q.size() == 2, arb_sequence_q[0] is S2's request and arb_sequence_q[1] is T1's request. [edit] Here's where the problem hits. Because the lock_list size() > 1, when the consumer (driver) calls get(), the sequencer will cycle through all its requests in its arb_sequence_q until it finds one that is ~is_blocked(). Unfortunately, that function cycles through all sequences in the lock_list regardless of whether the first item in the lock list corresponds to the request being processed. So since we have 7 locks in there, one for each thread, when the driver tries to get a new sequence, T1 will always be blocked by T2:T7. Similarly any request from T1:T7 will get locked out by the others. We've now deadlocked. I believe there is an issue here with the is_blocked() function which should have some form of priority encoding.
  17. Hi there IPXACT needs to capture array of registers properly in a design. Currently there is only one tag ''spirit:dim" to represent an array of registers. This does not enable us to capture an array of register effectively. Consider the following cases: 1. An array of registers can be one dimensional with each element offset by offset address 0x10. 2. An Array of multidimensional registers something like this: register_1[0][0] -> 0x0 register_1[0][1] -> 0x4 register_1[1][0] -> 0x10 register_1[1][1] -> 0x14 ... likewise Is there any way to capture just the address relationship to an array instance within IP-XACT XML tags? (Without using vendorExtensions tag?) We have not been able to capture the above said information inside IPXACT XML.(using only IP-XACT tags) Requesting thoughts regarding the same. Best regards Balasubramanian G
  18. Hello, I was wondering if are there any resources (papers, blogs, posts, best practices) about methodologies to implement UVM RAL for "large" designs (>100K registers and 50K rams)? I tried to do some research online but most of the results never cover "large" designs. I have experience using RAL and doing some customisation to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were "little" (1K regs and 100 rams) I'm interested on any information about aspects such as: Reg model re-usability and portability at sub-system and system level environments Performance: How heavy is the register model, since having this much registers may have a huge performance penalty over simulations Dynamic reconfiguration (I know in 1.2 once your model is locked not much can be done) RAM modelling in RAL (since it the uvm_mem is different from uvm_reg) Register Model Partitioning at block level Register Model limitations on real projects usage Implementation of different sized registers and non uniform mapping General RAL limitations Any material or hints on these topics is really appreciated Apologies for the broad question Thanks -R
  19. Hi, The purpose of this discussion is to understand different possibilities by which the simulation performance, memory usage can be increased. Scoreboard as we understand needs the data/packets/frames etc to be stored/buffered to do a comparison with the actual data out. This works out fine when we have small sized array ranging from few bytes to few thousands of bytes.. However imagine, if we have 100 thousands of bytes and above and there is a need to store them and lets say multiple of such lanes/flows , then this would take a hit on the simulation performance. And this gets worse if we have to reuse and port it to a subsytem/chip level simulations.. With this as the background, i am looking at alternate approach for scoreboards.. In a way is possible avoid scoreboard and check the data as it comes without the need to store the expected/input data. Approach that can be thought of : 1. Generating incremental data pattern and check at the output .. (Comes again with issues like aliasing etc.. and hence need to have longer patterns.) 2. Generation of PRBS stream as the payload of the frame.. and then have a PRBS checker at the output.. and see it remains locked.. (Debug would get worse with this.. if there is a mismatch) 3. Having a byte scoreboard.. something like that.. (Not sure how feasible this is). There are many challenges even with these approach.. I am just wondering if someone has already experienced such cases and what kind of challenges are thrown out.. Appreciate any input on this. Regards, svuvmuser !
  20. Hi All, I am a beginner in the field of hardware verification (1.5 yrs experience only). I have done couple of projects in UVM related to IPs such as UART and GPON. Now, i want to take up the next challenging (due to it's huge state space) self project - UVM based verification of a microprocessor. But i am unaware as to how should i begin? I searched the Web and there is so much material that i am totally confused. Can anybody share what should be my approach? How should i begin? Which microprocessor i should chose? From where can i get the DUT processor code? If anyone has implemented such project, could you please share the details. Thanks Krishna
  21. Hi All, I am working in verification. Where i have to generate reg_block for all the IP's using IPXACT. also top level reg_block which instantiates all the IP level register block using IPXACT. But i am not interested in Ports/Businterface/component. Please advise me what is the best method to do it. Thanks Saravanan
  22. Hi , To whom may correspond I think there is some kind of error in the UVM 1.1d register model. I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); uvm_reg_addr_t addrs[$]; uvm_reg_map system_map = get_root_map(); int unsigned bus_width = get_n_bytes(); uvm_reg_byte_en_t byte_en = -1; uvm_reg_map_info map_info; int n_bits; int lsb; int skip; int unsigned curr_byte; int n_access_extra, n_access; int n_bits_init; Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip); addrs=map_info.addr; // if a memory, adjust addresses based on offset if (rw.element_kind == UVM_MEM) foreach (addrs[i]) addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset; foreach (rw.value[val_idx]) begin: foreach_value uvm_reg_data_t value = rw.value[val_idx]; /* calculate byte_enables */ if (rw.element_kind == UVM_FIELD) begin int temp_be; int idx; n_access_extra = lsb%(bus_width*8); n_access = n_access_extra + n_bits_init; temp_be = n_access_extra; value = value << n_access_extra; while(temp_be >= 8) begin byte_en[idx++] = 0; temp_be -= 8; end temp_be += n_bits_init; while(temp_be > 0) begin byte_en[idx++] = 1; temp_be -= 8; end byte_en &= (1<<idx)-1; for (int i=0; i<skip; i++) void'(addrs.pop_front()); while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) void'(addrs.pop_back()); end curr_byte=0; n_bits= n_bits_init; The code continues but the interesting part is already there. Lets assume we have a register with 4 bytes and 1byte per address granularity (byte_addressing). Now, we do a FIELD access of 8bits length (the first byte of a register). The field is configured "individual_accessible, so UVM should only access that FIELD. The reg2bus should generate that byte request to be written. In other words, the vector "addrs" should have only one byte address. Going to the code, i see that initially the addrs has the 4 address ( the whole register) and when it comes to the "if (rw.element_kind == UVM_FIELD) begin" and it will pop_back()/remove all the exceeding bytes that doesn't need to complete "n_bits_init" of the field access. The problem is here: UVM has //while (addrs.size() > (n_bits_init/(bus_width*8) + 1)) and i think it should be while (addrs.size() > ((n_bits_init-1)/(bus_width*8) + 1)) //ejonalv possible error in UVM? check That is because in case we want to write 8 bits, it will calculate 8/8+1=2 address in the UVM version, but in fact it should require only 1 address. This is of course applicable for the READ variation. Did i misunderstand something? It is very hard to go through the register model without proper documentation in the code. I am looking forward your answer Best Regards Jonathan
  23. I am new to Synopsys VCS. I have been trying to simulate the testbench developed in UVM using VCS in command mode (Linux environment). But, I am not able to get the info displays and the output displays. I am have written the makefile using perl scritps. Can soemeone please tell me where I can find the detail example of using the options in my makefile to run it succesfully while viewing the output displays in command mode
  24. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  25. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
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