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Hello All, I have some doubts related to the relationship between PSEL and PENABLE signals in the APB Protocol. The specification informs that: The PENABLE signal is asserted the following clock after PSEL is asserted and de-asserted after a transfer takes place. I would like to understand about the following conditions: 1) Can PENABLE toggle while PSEL is de-asserted? 2) Can PENABLE be asserted in the IDLE and/or SETUP phase? 3) Can PSEL go log in to the SETUP phase? 4) What happens when PSEL is asserted high in the ACCESS phase and PENABLE is not de-asserted? Thanks
I am new to verification. Now I trying to verify a protocol like TCP/IP stack(mainly TCP over IP, without UDP, ICMP etc.). My first idea is that a golden Reference Model is needed. I generate sequences, send them to DUT through a driver, and monitoring my driver, get each transaction to RM, then I collect the response from both DUT and RM and compare them. But building such a RM would be very complex. My question is, do I really need a RM? What if I verify my DUT without any RM? For example, to verify DUT's feature of opening as client, my sequence can simply act as a server and do such routine: 1, send OPEN AS CLIENT command to DUT. 2, wait response from DUT, which should be a SYN. if not, assume test fail and exit. 3, send SYN ACK to DUT. 4, wait response from DUT, which should be an ACK. if not or wrong ACK, assume test fail and exit. 5, end, assume test pass.