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Is There An Existing Verification IP Core for AXI?

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I'm an RTL dev teaching myself UVM. 

I wrote a FIFO buffer to cross clock domains. 

The buffer has an AXI slave receiver for input and an AXI master transmitter for output. 

Here is my question:

Is there an existing UVM library I can use to verify an AXI widget I write? 


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  • 2 weeks later...

Several (EDA) companies are selling different flavors of AXI VIP. You might be able to find some open source VIP as well (just use your favorite search engine), but you might get no or limited support in case of issues / errors / questions.

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