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Found 4 results

  1. Hello Kindly support with the following question: Considering a verification environment that imports 2 packages, pkg_A and pkg_B. Both packkages contain some common class definitions (i.e. same class name, class properties, etc.): pkg_A.sv pkg_B.sv class some_name; class some_name; `uvm_object_utils(some_name) `uvm_object_utils(some_name) ,,,, ... This makes the same class name to be registered to the factory twice, leading to the : UVM_WARNING @ 0: reporter [TPRGED] Type name some_name already registered with factory. No string-based lookup support for multiple types with the same type name. Consider that both pkg_A and pkg_B have numerous class with same name. How can this be fixed? Thank you
  2. Does an abstract class (virtual class ....), which extends from uvm_object, benefit from using uvm utility macros (`uvm_component_utils, `uvm_object_utils)? As I understand, `uvm_component_utils and `uvm_object_utils are used to register a class w/ the factory so objects of that class can be overridden. But, because an abstract class cannot be instantiated, it cannot be overridden. Is that assessment correct? Are those utils macros doing smthg else besides allowing for 'overriding' capability? (Although I have looked at them, I know I don't fully understand all they're used for.) thanks, From uvm_object_defines.svh: //------------------------------------------------------------------------------ // // Title: Utility and Field Macros for Components and Objects // // Group: Utility Macros // // The ~utils~ macros define the infrastructure needed to enable the // object/component for correct factory operation. See <`uvm_object_utils> and // <`uvm_component_utils> for details. // // A ~utils~ macro should be used inside ~every~ user-defined class that extends // <uvm_object> directly or indirectly, including <uvm_sequence_item> and // <uvm_component>. // // Below is an example usage of the ~utils~ macro for a user-defined object. // //| class mydata extends uvm_object; //| //| `uvm_object_utils(mydata) //| //| // declare data properties
  3. Hi, all I want to use the factory mechanism to write one reusable test, this is the codes class my_test #(parameter TSID=0) extends uvm_test; typedef my_test #(TSID) this_typ; typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; static function type_id get_type(); return type_id::get(); endfunction : get_type function new(string name = "my_test", uvm_component parent=null); super.new(name,parent); endfunction : new ... endclass But I met such a compile error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: $sformatf("my_test%0d", TSID) Source info: typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; ... If the second parameter should be a constant or constant expression in typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; then how can i distinguish the specialized test using TSID which is from run option (my original idea is that using parameter TSID to distinguish the different specialized test)? Second problem, my_test is a generic class now, where should the specialized test define and how to define if my original idea is feasible? Regards
  4. I'm attempting to do an instance override on a parametrized type in UVM, but I can't seem to set a correct path to the instance I want to override. The code below factory.set_inst_override_by_type(typical_item#(1, 1)::get_type(), typical_item_1#(1, 1)::get_type(), override_path); works if override_path == "*" which is matching everything and thus doing in essence a type override - not what I want. If I try to be more specific (even entering something like uvm_test_top) no instances are overridden. Is there a way to find out the correct instance path to some sequence so I can use it in my override call?
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