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Found 4 results

  1. Hi, The purpose of this discussion is to understand different possibilities by which the simulation performance, memory usage can be increased. Scoreboard as we understand needs the data/packets/frames etc to be stored/buffered to do a comparison with the actual data out. This works out fine when we have small sized array ranging from few bytes to few thousands of bytes.. However imagine, if we have 100 thousands of bytes and above and there is a need to store them and lets say multiple of such lanes/flows , then this would take a hit on the simulation performance. And this gets
  2. Hello, I am developing a verification environment for a DUT that has cache memory in it. I would like to model that memory in my environment and make it accessible to various components at different levels of hierarchy. What is the best way to add "hooks" for the same? This is what my env looks like. class top_env extends ovm_env; `ovm_component_utils(top_env) mem_model mem_model_h; scoreboard scoreboard_h; checker checker_h; endclass I want the mem_model to be accessible to all the components in the design at any given time. I
  3. For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For example this ready signal is getting low at clockno 8 and it should remain low for clockno 9 and 10 and the clockno 11 the signal will be high as per the slave configuration. when the multiple burst transacion occurs with (write length > 2) the ready signal behavior will be like above. I want to write a functional coverage like "wready" and next "wready" signal latency is 2 which means when the
  4. Which is best method to start , randomize and end the sequence among the `uvm_do, start_item, `uvm_create, `uvm_send and the others and why? Please explain.
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