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Showing results for tags 'simulation'.
Hi all, I guess this is a basic question but I can't find the answer. I have a SystemC module that performs several complex arithmetic operation ( several multiplication ). When I simulate it I can see it performs all those operations in on clock cycle after I provided the input. I'm pretty sure that when I'll feed the HLS tool, the tool will pipeline the operation adding latency. Is there any way to manually add latency in order to match what I guess will be the result of the HLS ? I guess I can simulate the latency changing the SC_METHOD with a SC_THREAD and adding a sort of counter, bu
Hi all, I have a couple of counters in my monitor's run_phase which I'm trying to print in the report_phase. But, the test itself is being killed (I cannot edit the file which is killing the test) which my monitor is still in the run_phase & hence the counters aren't being printed. Is there any way to enforce the report_phase to be run/ any way to call the report_phase from within the monitor file ?