RAL Backdoor write

[ripal]

Hi ,

We are trying to do backdoor one of the register in our RAL and set hdl path using add_hdl_path_slice fucntion. 

Will take similar example here. say we have 32 bit REG1. REG1 has two fields F1 and F2 each of 16 bits. 

We have set below HDL path :

REG1.add_hdl_path_slice("IP.REG.regout", 0,16);

REG1.add_hdl_path_slice("IP.REG.regout", 16,16);

 

When we write through REG1.poke and read back , we see only value deposited by last slice. If we deposit value 0x12345678, while reading back , it returns value 0x1234 only. Looks like it overrides value written by previous slice.

Question is  it necessary to provide bit range in first argument of add_hdl_path_slice ?  Or UVM will take care of that ? 

If we set below path as add_hdl_path_slice , then it works fine and returns correct value 0x12345678.

REG1.add_hdl_path_slice("IP.REG.regout[15:0]", 0,16);

REG1.add_hdl_path_slice("IP.REG.regout[31:16]", 16,16);

 

[mastrick]

I believe the UVM intent of 

Quote

REG1.add_hdl_path_slice("IP.REG.regout", 16,16);

is to associate the (whole) signal "IP.REG.regout" with the 16 bits starting at offset 16 of the data in the reg model.  The start and offset do not affect the signal, and so you do need to provide the bit range as you show to associate a slice of the signal with a slice of the internal data.  I agree the documentation does not make that clear, and I have filed a Mantis to improve that documentation.

[ripal]

Thanks for clarification mastrick.