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Showing results for tags 'disable condition'.
I recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello Wor