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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. How to dump data into a file in UVM

    By Subramanian R,
    • 1 reply
    • 6.7k views

  2. Problems creating objects in the "new" phase of a cofig object

    By kam.zamani,
    • 3 replies
    • 3.5k views

  3. Should uvm_hdl_force_time be declared automatic?

    By lanfranco.salinari,
    • 3 replies
    • 2.2k views

  4. 'run' phase is ready to proceed to the 'extract' phase

    By diju.ms,   
    • 0 replies
    • 3.6k views

  5. SystemVerilog and pthreads

    By nizam.ahmed,
    • 2 replies
    • 2.6k views

  6. Possible contradiction in SV standard

    By tudor.timi,   
    • 2 replies
    • 2.1k views

  7. Program block: doesn't need to be instantiated? $finish called after all threads done.

    By ljepson74,   
    • 5 replies
    • 2.9k views

  8. multiple SystemC tops in UVM_ML

    By matteodc,
    • 3 replies
    • 1.7k views

  9. Help Required for Scoreboard Code

    By shine2828,
    • 1 reply
    • 2.9k views

  10. ISSUE with 11.4.14 Streaming operators (pack/unpack) if the size of source not even

    By karandeep963,
    • 4 replies
    • 3k views

  11. Exiting simulation after some delay when errors exceed max_quit_count

    By ujjalbose,
    • 2 replies
    • 6.6k views

  12. Asynchronous driving/monitoring in a SV-UVM framework

    By sara_m141,   
    • 5 replies
    • 2.4k views

  13. How to lock the sequencer from the driver

    By youngzi,   
    • 1 reply
    • 3.4k views

  14. Reading a binary file in UVM - $fread

    By apafi_adi,
    • 4 replies
    • 12.1k views

  15. Passing bit width parameters from top module to sequence item classes

    By kate,   
    • 1 reply
    • 3k views

  16. conditionnal import package in SV

    By JP LM,
    • 1 reply
    • 3.5k views

  17. How to use SVA check different clock delay

    By Meng Zhang,   
    • 0 replies
    • 1.9k views

  18. Program blocks

    By amitk3553,   
    • 5 replies
    • 7.1k views

  19. Is there any obligation in using dynamic delay while starting the sequences

    By karandeep963,
    • 9 replies
    • 3.3k views

  20. Can we perform UVM_REG read/write access based on Address?

    By balasubramanian.g@pmcs.com,   
    • 3 replies
    • 15.3k views

  21. "Mixin" classes - parametrizing the base class

    By alangloria,
    • 11 replies
    • 7.5k views

  22. Pointer passing across multi-language boundaries - SC<->SV

    By karandeep963,   
    • 0 replies
    • 1.2k views

  23. who can interpret use of soft constraint ?

    By wszhong631,
    • 3 replies
    • 2.2k views

  24. print internal variables of property in sva

    By Attaluri,
    • 4 replies
    • 5.2k views

  25. Using $past in procedural code

    By tudor.timi,
    • 1 reply
    • 5.2k views
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