interface module with TLM2 interface

[Khushi]

Hi Guys

I am trying to put in place  a generic UVM verification env for TLM IPs. For RTL IPs we usually define the interface like(for simple adder)

interface dut_if (input clk);
    logic [3:0] in1;
    logic [3:0] in2;
    logic [4:0] out;
endinterface

What the interface definition look like for TLM2 interfaces (for example if DUT has a target socket)

Thanks

Khushi

[David Black]

TLM2 is completely different from RTL type of connection. Interface won't work. Nor is there timing you can count on since it could be either AT or LT without timing.

You also need to specify if you are interfacing between SV and SC or is this native SV UVM to UVM TLM2.