parsing using system verilog

[iidolevy]

Hi,

I have an IP with built in tests, written in pyhton.

I want to parse those tests and use them in higher level (uvm testbench). Eventually each test will be a uvm sequence.

For that I need a system verilog parser.

Is there a reference that I can use for this purpose?

example for lines in existing test:

 

WriteBlock SLAVE 0x0000ffff

Data 8

a5a5a5a5 ffffffff 

 

Thanks

 

 

[bhunter1972]

SV isn't the best language to parse with, but Python is!  You should consider having your Python script output real SystemVerilog code that can then be loaded into the simulator instead.

 

Consider:

 

for (addr, data) in write_commands:
   print >>sv_file, "   block.write_data('h%s, 'h%s);" % (to_hex(addr), to_hex(data))

etc.

[Tyson]

Hi

Bhunter1972, 

''SV isn't the best language to parse with, but Python is!  You should consider having your Python script output real SystemVerilog code that can then be loaded into the simulator instead.''

Maybe my question is slightly off topic.  I am using a tool to generate parser in Python from very simple functional requirements. I have made a grammar for my DUT requirements. The requirements are one line text files.  The DUT is in SV. I am using tool to generate python parser because based on my requirements I want to generate one SV test bench for my SUV DUT. Do you think somewhere I can introduce python scripting to generate a SV TB after generating python parser from my requirements grammar ?

Thanks !