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Found 3 results

  1. With the following code, import uvm_pkg::*; `include "uvm_macros.svh" class seq_data extends uvm_sequence_item; `uvm_object_utils(seq_data) rand bit [7:0] addr; rand bit [7:0] data; constraint c_addr {addr >=1000;addr<2000;} constraint c_data {data >=0000;data<=4000;} function new (string name = "",uvm_component parent=null); super.new(name); endfunction virtual function void display (); `uvm_info (get_type_name (), $sformatf ("addr = 0x%0h, data = 0x%0h", addr, data), UVM_LOW); endfunction endclass class my_test extends uvm_test; `uvm_component_utils(my_test) seq_data my_data; function new(string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); my_data = seq_data::type_id::create("my_data",this); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); repeat(4) begin #10; assert(my_data.randomize()); my_data.display(); end phase.drop_objection(this); endtask endclass module top; initial begin run_test("my_test"); end endmodule I am getting the following error xmsim: *E,ASRTST (./example.sv,38): (time 30 NS) Assertion worklib.$unit_0x762d41ec::my_test::run_phase.__assert_1 has failed UVM_INFO example.sv(17) @ 30: reporter@@my_data [seq_data] addr = 0x0, data = 0x0 assert(my_data.randomize()); | xmsim: *W,SVRNDF (./example.sv,38|32): The randomize method call failed. The unique id of the failed randomize call is 3. Observed simulation time : 40 NS + 0 xmsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints: constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) xmsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints: rand variables: addr [./example.sv, 6] I am not seeing any constraint with the following expression constraint c_addr {addr >=1000;addr<2000;} (./example.sv,9) Can someone help me to understand what is going wrong here ? Thanks Khushi
  2. Hi All, I have a typical use case, where the sequence item w.r.t driver is always the same, but it's view needs to change while writing constraints. The fields of sequence items to write constraints change w.r.t the header type, there are around 25-30 types of headers. What is the best way to create the base sequence item in this case in line with UVM methodology? Example:- bit [32] header; //Actual header as seen by driver The format of the header is however dynamic:- format-1 : bit[31:21] header_type; bit[20:10] field_2_type_1; bit[9:0] field_3_type_1; format-2: bit[31:21] header_type; bit[20:15] field_2_type_2; bit[14:8] field_3_type_2; bit[7:0] field_4_type_2; format-3: bit[31:21] header_type; bit[20:12] field_2_type_3; bit[11:6] field_3_type_3; bit[5:0] field_4_type_3; ....... ...... I currently have though of a packed union of different structures to be one of the solutions for this type of scenario. This union will be a member of the sequence_item class and the structure will be representation of the different formats of header. Is there a better means of creating polymorphic sequence items in UVM. I am ok to try some system verilog hacks in uvm too for a solution.
  3. I am using QuestaSim 10.3a_1 and try to record a dynamic array in the sequence item. But it doesn't show in the waveform window. When I try to fix the array size and use uvm_field_sarray_int to record it, it works well and data show as expected in the waveform windows. My code: # sequence item parameter int P_BIT_DEPTH = 10; rand int unsigned data_len; rand bit unsigned [P_BIT_DEPTH-1:0] data []; ... `uvm_field_array_int(data, UVM_ALL_ON+UVM_UNSIGNED) `uvm_field_int (data_len, UVM_ALL_ON+UVM_UNSIGNED) ... constraint c_data_size { data.size() == data_len; }; constraint c_data_size_order { solve data_len before data; }; # Sequence body task start_item(req); if (! req.randomize() with { data_len == 2; }) `uvm_error(tID, "Can't randomize ingress packet") finish_item(req); req.sprintf() always prints the right information, no matter data is dynamic or static array.
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