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Khushi

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  1. Hi Erwin Thanks for your comments. Is it something which is mentioned in section 3.1.6 in https://www.accellera.org/images/downloads/standards/ip-xact/IP-XACT_User_Guide_2018-02-16.pdf Thank Khushi
  2. Hi Which element is IP-Xact is translated to uvm_reg_map in UVM ? In IP-xact, I have a slave interface(e.g. APB) to configure the registers(read/write). This slave interface has a memory map reference. In that memory map there are two address block and each address block has a set of registers. From here: IPxact registers => uvm reg IPxact register block => uvm reg block IPxact memory map => ?? ?? => uvm_reg_map. Thanks in advance Khushi
  3. In IP-Xact there is a section localMemoryMap inside address space which looks similar to the memoryMap. I am not sure to understand the difference between the two and what should be used and when. Can you help me on this ? Also in IP-xact, is it possible to define a register somewhere and instantiate it or use it at other places ? Thanks Khushi
  4. Hi I have a set of registers which can be accessed from two different addr maps (uvm_reg_map) and both sees these addresses at different address. We are trying to generate such uvm registers through IP-Xact. In IP-Xact I can specify registers/register blocks but I am not sure how to specify the fact that one register/register block can be seen at different address via different map/interface. How I can specify the uvm_reg_map in IP-Xact ? Any clue/example help on this please ? Thanks Khushi
  5. Hi I am trying to understand whileBoxElement in IP-XACT and its usage. Can someone explain this and provide some examples. Thanks
  6. Hi Erwin If I am correct, even in 1685-2009 we can describe RTL and TLM within the same component using two different views. Am I correct ? I have a scenario where I have an RTL IP with an optional port which is only present in one view(e.g. simulation view). can I use two view in such case and use viewnameref with that optional port ? Why I need to explicitly specify the typeName with wireTypeDef. In this specific case I want to use native types even when I have optional ports. Is it intentional to have typename mandatory ? How to manage two different businterfaces then ? I hav
  7. Hi Edwin, I understand your point but if both A.a and B.b map the clock signal and if we just connect A.a to B.b,should the tool connect the clock or not ? with error or without error ?. In general during interface connections, what happens to pins which has same direction on both sides ? Should tool connect them ? or left them unconnected ? with or without error/warning? Thanks Khushi
  8. Thanks Edwin. Currently we are in IP-Xact 2009. Is there a way to do this in 2009 ? Thanks Khushi
  9. Hi Edwin Thanks for your comment and links to ARM busdefs. I didn't understand the following Normally both clock and reset are "in" on both master and slave interfaces. So when you connect master to slave then - either the tool reports an error saying can not connect two ports with same direction - or ther tool just skip the connections with a warning and later we can do some adhoc connections In your environment, you mentioned the clock and reset physical ports are mapped in component master/slave bus interface with other protocol signals. In this case how you
  10. Hi Erwin Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts. I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ? Thanks Khushi
  11. Hi Erwin, If I see the AMBA busdef AMBA_IP-XACT-1.4_BusDefinitions_2011_10_21\amba.com\AMBA4\AXI4\r0p0_0, I see for both ACLK and ARESETn, the presence element is required in both onMaster and onSlave Here you want to say something else ? =========================================================== To summarize my understanding regarding the clock and reset stuff. -a) We should list the clock and reset in protocol abstraction definition -b) We should set presence => optional for both clock and reset in both onMaster and onSlave -c) In component businterfac
  12. Hi I have a design(top) with two instances of a subsystem(ss). In the subsystem(ss) I have an instance of a component(cmp). My design instances looks like top top.ss1 top.ss1.cmp top.ss2 top.ss2.cmp The component (cmp) is a generic component,(lets say a memory which has a generic parameter SIZE and during the instantiation of that component we specify the SIZE for that instance). I created a component and specify the SIZE as model parameter. Then I created a subsystem design with an instance of component cmp and specify the SIZE parameter in IP-Xact desi
  13. Thanks Erwin for the nice explanation. I have an additional question here. As you mentioned system interfaces are used to connect clock, reset and sidebands signals. How the system interfaces are helpful to connect these ? Are they provide some extra capabilities which is not there if we use normal(master/slave) interface connections or adhoc connections. How the system group name in busdefs for the system bus interfaces are used in net-listing. Thanks Khushi
  14. Thanks Erwin for the detail explanation. In almost all protocols we have clk and rst signals which are "in" on both master and slave. So does it mean for all such protocols the corresponding bus interface in component should be always mirroredSlave(instead of master) and mirroredMaster(instead of slave) Or we should not map clk and reset in component bus interface and keep them as master or slave (instead of mirroredSlave or mirroredMaster) Thanks Khushi
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