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About Khushi

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  1. Hi Folks Any help on this ? Thanks Khushi
  2. Hi I am trying to understand whileBoxElement in IP-XACT and its usage. Can someone explain this and provide some examples. Thanks
  3. Hi Erwin If I am correct, even in 1685-2009 we can describe RTL and TLM within the same component using two different views. Am I correct ? I have a scenario where I have an RTL IP with an optional port which is only present in one view(e.g. simulation view). can I use two view in such case and use viewnameref with that optional port ? Why I need to explicitly specify the typeName with wireTypeDef. In this specific case I want to use native types even when I have optional ports. Is it intentional to have typename mandatory ? How to manage two different businterfaces then ? I have an AHB bus in RTL and TLM2 bus in TLM. Do I need to describe both businterfaces in IP-Xact ? Thanks Khushi
  4. Hi Edwin, I understand your point but if both A.a and B.b map the clock signal and if we just connect A.a to B.b,should the tool connect the clock or not ? with error or without error ?. In general during interface connections, what happens to pins which has same direction on both sides ? Should tool connect them ? or left them unconnected ? with or without error/warning? Thanks Khushi
  5. Thanks Edwin. Currently we are in IP-Xact 2009. Is there a way to do this in 2009 ? Thanks Khushi
  6. Hi Edwin Thanks for your comment and links to ARM busdefs. I didn't understand the following Normally both clock and reset are "in" on both master and slave interfaces. So when you connect master to slave then - either the tool reports an error saying can not connect two ports with same direction - or ther tool just skip the connections with a warning and later we can do some adhoc connections In your environment, you mentioned the clock and reset physical ports are mapped in component master/slave bus interface with other protocol signals. In this case how you connect these with clock and reset driver without a phantom port ? Thanks Khushi
  7. Hi Erwin Thanks for the explanation. It clears a lot of doubts. I really appreciate your efforts. I have one more related questions. If I have a component with I2C master interface and another component with I2C slave interfaces. As I2C interface is asymetric, so I cannot connect master to slave directly. In this case how these two component can be connected. Do we need some extra abstractor/bridge or phantom component with mirrored interfaces here to make the connections ? Thanks Khushi
  8. Hi Erwin, If I see the AMBA busdef AMBA_IP-XACT-1.4_BusDefinitions_2011_10_21\amba.com\AMBA4\AXI4\r0p0_0, I see for both ACLK and ARESETn, the presence element is required in both onMaster and onSlave Here you want to say something else ? =========================================================== To summarize my understanding regarding the clock and reset stuff. -a) We should list the clock and reset in protocol abstraction definition -b) We should set presence => optional for both clock and reset in both onMaster and onSlave -c) In component businterface, we can either map the physical clock and reset to busdef logical ports or not 1) if we map, then we should use phantom component strategy as you explained in ( https://forums.accellera.org/topic/6446-interface-mode-mirroredmaster-mirroredslave/ ) 2) if we not map, then either we connect clock and reset as adhoc or create clock and reset businterface in component and create interface connections for clock and reset (what is recommended here ??) Please let me know if my understanding is correct. Thanks Khushi
  9. Hi I have a design(top) with two instances of a subsystem(ss). In the subsystem(ss) I have an instance of a component(cmp). My design instances looks like top top.ss1 top.ss1.cmp top.ss2 top.ss2.cmp The component (cmp) is a generic component,(lets say a memory which has a generic parameter SIZE and during the instantiation of that component we specify the SIZE for that instance). I created a component and specify the SIZE as model parameter. Then I created a subsystem design with an instance of component cmp and specify the SIZE parameter in IP-Xact design(configurable element value). I instantiate that subsystem as ss1 in top. So far so good. Now I have to instantiated the same subsystem as ss2 in same top and in top.ss2.cmp.SIZE parameter value is different then top.ss1.cmp.SIZE. The cmp SIZE value is specified while creating the cmp instance in subsystem component. Here I stuck because I do not find a way to have different values of top.ss1.cmp.SIZE and top.ss2.cmp.SIZE. Is there a way to do this in Ip-Xact ? Thanks Khushi
  10. Thanks Erwin for the nice explanation. I have an additional question here. As you mentioned system interfaces are used to connect clock, reset and sidebands signals. How the system interfaces are helpful to connect these ? Are they provide some extra capabilities which is not there if we use normal(master/slave) interface connections or adhoc connections. How the system group name in busdefs for the system bus interfaces are used in net-listing. Thanks Khushi
  11. Thanks Erwin for the detail explanation. In almost all protocols we have clk and rst signals which are "in" on both master and slave. So does it mean for all such protocols the corresponding bus interface in component should be always mirroredSlave(instead of master) and mirroredMaster(instead of slave) Or we should not map clk and reset in component bus interface and keep them as master or slave (instead of mirroredSlave or mirroredMaster) Thanks Khushi
  12. Hello I am referring to selction 5.13 Clock and reset handling in IEEE 1685-2009. With this I have few questions. I have a bus protocol for which I need to create a busdef/absdef pair. For example lets say I am creating AXI busdef/absdef pair. In my component I have an AXI master and a AXI slave interface. The clock and reset for both the interfaces have common driver. In this context, I am not sure - if I should list clock and reset in corresponding absdef or not. If yes should I leave them un-mapped in corresponding bus interface in component so that these are not connected when I connect this bus interface to other side ? - in the component IP-Xact should I create a separate bus inteface for reset and clock ? In general almost all protocols are dependents on clock and reset. In this case what are the general guidelines and recommended ways for clock and reset handling. Thanks Khushi
  13. I believe registerFile concept in IP-Xact can handle the 2 dimensional registers as Ankit specified above.
  14. Hi When we should use system businterface in IP-Xact and how an EDA behaves when it sees system businterface vs master/slave ? Thanks Khushi
  15. Hi Can anyone explain me when to use mirroredMaster and mirroredSlave interface mode in IP-Xact businterfaces. I am not able to understand when to use master vs mirroredSlave (or slave vs mirroredmaster). I have a set of bus protocols for which I created a set of busdef/absdef but in component I am not able to decide whether to use master vs missoredSlave and slave vs mirroredMaster. Can someone explain here in layman terms the different between master and mirroredSlave (slave vs mirroredmaster) and when to use mirror interfaces and what is the consequence in generated netlist. Thanks Khushi
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