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Showing results for tags 'register model'.
Found 7 results
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I am trying to verify 8 bit RW registers and in some of the registers 4 bits are RESERVED lets say [3:0] . My bit bash sequence tries to write in these constant bit and flags me a mismatch error in the DUT and Mirrored Value. How do i stop my bit bash sequence from checking these RESERVED bits of a register. Thanks for your help -
Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks. -
I have recently modeled registers as simple unions to represent bitfields, for example: typedef union { struct { uint32_t ADDRESS:5; uint32_t RESERVED:26; uint32_t ENABLE:1; } b; uint32_t w; } register_type; which facilitates the access to either the complete word or a bitfield. The interesting part comes when I try to check if the register value has changed, is there a more elegant way of doing this than polling in if or while statements for each register's value? I need to do this for a lot of them so I was wondering if modeling this using sc_bv provides a built-in eve
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Hi , To whom may correspond I think there is some kind of error in the UVM 1.1d register model. I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh task uvm_reg_map::do_bus_write (uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter); uvm_reg_addr_t addrs[$]; uvm_reg_map system_map = get_root_map(); int unsigned bus_width = get_n_bytes(); uvm_reg_byte_en_t byte_en = -1; uvm_reg_map_info map_info; -
Hi, I am using uvm standard register model , register adapter (bus2reg & reg2bus) to send and receive transaction to ral model and DUT. and it is working fine if i do single read and write.(means i perform the 32 bit read n write using reg.read(status,address,data)reg.write(status,address,data)) My challange is that i have to perform the more than 32 bit transaction which performs the read and write on multiple registers, If there any way to use the same reg.read/write method to perform more than one register -
Version 5.0
327 downloads
This download contains a sample UVM environment that shows the use of IDesignSpec Free to generate a UVM Register Model. The input can be SystemRDL, IP-XACT, Word, Excel, XML etc. You can download the Free IDesignSpec Register Generator from here. You can use the included example as a ready reference to generate your own register model. You can use any or all of the IDesignSpec flavors: Word, Excel or Batch. -
Hi Guys, I am using UVM Register model to mimmick RTL's register implementation. Some registers are not implemented in RTL which are going to be connected to output port of some other module. I have got a HDL path of register as an output port declaration of some module. Something like: The HDL path is: "tb_top.dut_u.interrupt_module_u.o_ext_interrupt" o_ext_interrupt is declared as output port inside interrupt_module, which is not connected to any other wire or register. Can this output port's value be changed by writing to it via UVM BACKDOOR ? I am using following A
